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Sidecar Mainboard FPGA: add proper c/d image #1906
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before
after
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I tested this fix on a Sidecar D in manufacturing. Here is the output from the offending commit:
Here is the output running an image from the commit prior to the offending commit:
Then again, with this fix:
@jclulow note that I'm running the final test with a locally built humility as Hubris main now requires support for v9. |
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lgtm
This fixes a problem I accidentally introduced back in 4b74549, meaning it was part of Sidecar release v1.0.29 and R11. There's no meaningful impact to customers from this problem.
In that update, I accidentally copied the Rev B bitstream to both
sidecar_mainboard_rev_b.bit
andsidecar_mainboard_rev_c_d.bit
. The result is that rev C/D Sidecars are running the rev B FPGA image. In practice this means very little, as the only meaningful change in FPGA-land is that we added a 36th Ignition link, the link between the controller and the target on its own board. At this time nothing is paying attention to any of that except our loopback test fixture in manufacturing (where this problem was caught).Obviously this highlights our current manual process of getting FPGA images into our Hubris image releases. We should certainly have a discussion about how to add automation (or at very least checks!) to make this process less error-prone!
@labbott @jclulow with my apologies, we will need to get this released and deployed into manufacturing. We can coordinate that in chat. In the meantime, I will instruct the test engineers to ignore Ignition Port 35 errors for now as that is caused by this bug.