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    • riscv-b

      Public
      "B" extension - that represents the collection of the Zba, Zbb, and Zbs extensions
      Makefile
      Creative Commons Attribution 4.0 International
      4401Updated Dec 11, 2024Dec 11, 2024
    • RISC-V Instruction Set Manual
      TeX
      Creative Commons Attribution 4.0 International
      6523.7k20916Updated Dec 11, 2024Dec 11, 2024
    • Obviating Memory-Management Instructions after Marking PTEs Valid (Svvptc)
      Makefile
      Creative Commons Attribution 4.0 International
      4200Updated Dec 11, 2024Dec 11, 2024
    • Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
      Makefile
      Creative Commons Attribution 4.0 International
      50253414Updated Dec 11, 2024Dec 11, 2024
    • This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.
      Makefile
      Creative Commons Attribution 4.0 International
      1211Updated Dec 11, 2024Dec 11, 2024
    • Zilsd (Load/Store Pair for RV32) Fast-Track Extension
      Makefile
      Creative Commons Attribution 4.0 International
      4700Updated Dec 11, 2024Dec 11, 2024
    • Makefile
      65102Updated Dec 11, 2024Dec 11, 2024
    • The Zabha extension provides support for byte and halfword atomic memory operations.
      Makefile
      Creative Commons Attribution 4.0 International
      8800Updated Dec 11, 2024Dec 11, 2024
    • GitHub repository for the Functional Safety SIG Whitepaper Development
      TeX
      Creative Commons Attribution 4.0 International
      1100Updated Dec 11, 2024Dec 11, 2024
    • This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
      Python
      Creative Commons Attribution 4.0 International
      31584012Updated Dec 11, 2024Dec 11, 2024
    • Documentation developer guide
      TeX
      Creative Commons Attribution 4.0 International
      349442Updated Dec 11, 2024Dec 11, 2024
    • riscv-cfi

      Public
      This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. and Unpriv. specifications at https://github.com/riscv/riscv-isa-manual
      Makefile
      Creative Commons Attribution 4.0 International
      228600Updated Dec 11, 2024Dec 11, 2024
    • This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
      Makefile
      Creative Commons Attribution 4.0 International
      51701Updated Dec 10, 2024Dec 10, 2024
    • CSS
      Creative Commons Attribution 4.0 International
      163231Updated Dec 10, 2024Dec 10, 2024
    • Working Draft of the RISC-V Debug Specification Standard
      Python
      Other
      93461608Updated Dec 10, 2024Dec 10, 2024
    • Sail RISC-V model
      Coq
      Other
      1704789063Updated Dec 10, 2024Dec 10, 2024
    • The Ssdtso is a fast-track extension adding a 'dynamic-RVTSO' mode of operation and on-demand per-hart switching between the memory models.
      Makefile
      Creative Commons Attribution 4.0 International
      2101Updated Dec 10, 2024Dec 10, 2024
    • Dot-Product Extension
      Makefile
      Creative Commons Attribution 4.0 International
      4433Updated Dec 10, 2024Dec 10, 2024
    • docs-spec-template

      Public template
      Makefile
      Creative Commons Attribution 4.0 International
      212432Updated Dec 9, 2024Dec 9, 2024
    • A base container image populated with the dependencies to build the RISC-V Documentation.
      Apache License 2.0
      8904Updated Dec 9, 2024Dec 9, 2024
    • OpenEmbedded/Yocto layer for RISC-V Architecture
      BitBake
      Other
      143368171Updated Dec 4, 2024Dec 4, 2024
    • This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.
      Makefile
      Creative Commons Attribution 4.0 International
      184321Updated Dec 4, 2024Dec 4, 2024
    • RISC-V Performance Events Specification
      Python
      Creative Commons Attribution 4.0 International
      3452Updated Dec 4, 2024Dec 4, 2024
    • This repository holds the front matter pages for the RISC-V Library
      1100Updated Dec 3, 2024Dec 3, 2024
    • Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores
      Makefile
      Creative Commons Attribution 4.0 International
      3760Updated Dec 2, 2024Dec 2, 2024
    • RISC-V Opcodes
      Python
      BSD 3-Clause "New" or "Revised" License
      3057032726Updated Nov 27, 2024Nov 27, 2024
    • The Timing Fences Task Group proposes an ISA extension to mitigate timing channels by partitioning shared microarchitectural states.
      TeX
      Creative Commons Attribution 4.0 International
      652000Updated Nov 26, 2024Nov 26, 2024
    • The ISA specification for the Zalasr extension.
      Makefile
      Creative Commons Attribution 4.0 International
      2231Updated Nov 23, 2024Nov 23, 2024
    • guides

      Public
      RISC-V International Guides
      Creative Commons Zero v1.0 Universal
      0000Updated Nov 18, 2024Nov 18, 2024
    • riscv-aia

      Public
      Makefile
      Creative Commons Attribution 4.0 International
      2083281Updated Nov 15, 2024Nov 15, 2024