wip

data/xyloni.isf

@@ -0,0 +1,54 @@
+# Efinity Interface Configuration
+# Version: 2023.1.150
+# Date: 2023-10-06 23:12
+#
+# Copyright (C) 2017 - 2023 Efinix Inc. All rights reserved.
+#
+# Device: T8F81
+# Package: 81-ball FBGA (final)
+# Project: xyloni
+# Configuration mode: active (x1)
+# Timing Model: C2 (final)
+
+
+# Device setting
+design.set_device_property("1A","VOLTAGE","3.3","IOBANK")
+design.set_device_property("1B","VOLTAGE","3.3","IOBANK")
+design.set_device_property("1C","VOLTAGE","1.1","IOBANK")
+design.set_device_property("2A","VOLTAGE","3.3","IOBANK")
+design.set_device_property("2B","VOLTAGE","3.3","IOBANK")
+
+# Create instance
+design.create_pll_input_clock_gpio("PLL_IN")
+design.create_input_gpio("i_rst")
+design.create_output_gpio("l2")
+design.create_output_gpio("l3")
+design.create_output_gpio("l4")
+design.create_output_gpio("o_uart_tx")
+design.create_output_gpio("q")
+design.create_block("pll_inst1","PLL")
+
+# Set property, non-defaults
+design.set_property("o_uart_tx","OUT_REG","REG")
+design.set_property("o_uart_tx","OUT_CLK_PIN","i_clk")
+design.set_property("pll_inst1","CLKOUT0_EN","1","PLL")
+design.set_property("pll_inst1","CLKOUT1_EN","0","PLL")
+design.set_property("pll_inst1","CLKOUT2_EN","0","PLL")
+design.set_property("pll_inst1","CLKOUT0_DIV","8","PLL")
+design.set_property("pll_inst1","CLKOUT0_PIN","i_clk","PLL")
+design.set_property("pll_inst1","LOCKED_PIN","i_pll_locked","PLL")
+design.set_property("pll_inst1","M","16","PLL")
+design.set_property("pll_inst1","N","1","PLL")
+design.set_property("pll_inst1","O","4","PLL")
+design.set_property("pll_inst1","REFCLK_FREQ","33.33","PLL")
+design.set_property("pll_inst1","RSTN_PIN","","PLL")
+
+# Set resource assignment
+design.assign_pkg_pin("PLL_IN","C3")
+design.assign_pkg_pin("i_rst","C5")
+design.assign_pkg_pin("l2","J6")
+design.assign_pkg_pin("l3","D7")
+design.assign_pkg_pin("l4","D8")
+design.assign_pkg_pin("o_uart_tx","F3")
+design.assign_pkg_pin("q","B3")
+design.assign_resource("pll_inst1","PLL_0","PLL")

servant.core

@@ -197,6 +197,11 @@ filesets:
       - servant/servant_upduino2.v : {file_type : verilogSource}
       - data/upduino2.pcf : {file_type : PCF}
 
+  xyloni:
+    files:
+      - data/xyloni.isf: {file_type : ISF}
+      - servant/servant_xyloni.v : {file_type: verilogSource}
+
   zcu106:
     files:
       - servant/servus_clock_gen.v : {file_type : verilogSource}
@@ -558,6 +563,17 @@ targets:
       - with_csr=1
     toplevel : servant_sim
 
+  xyloni:
+    filesets: [mem_files, soc, xyloni]
+    flow: generic
+    flow_options:
+      tool: efinity
+      family: Trion
+      part: T8F81
+      timing: C2
+    parameters : [memfile, memsize]
+    toplevel : servant_xyloni
+
   zcu106:
     default_tool: vivado
     description : Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit

servant/servant_xyloni.v

@@ -0,0 +1,46 @@
+`default_nettype none
+module servant_xyloni
+(
+ input wire  i_clk,
+ input wire  i_pll_locked,
+ input wire  i_rst,
+ output wire o_uart_tx,
+ output wire l2,
+ output wire l3,
+ output wire l4,
+ output wire q);
+
+   assign l4 = i_pll_locked;
+   assign l3 = i_rst;
+
+   parameter memfile = "zephyr_hello.hex";
+   parameter memsize = 8192;
+
+   wire      wb_clk;
+   wire      wb_rst;
+
+reg [3:0] rstreg = 4'b1111;
+
+always @(posedge i_clk) begin
+    if (i_pll_locked) rstreg <= {rstreg[2:0],~i_rst};
+    else rstreg <= 4'b1111;
+end
+
+   assign o_uart_tx = q;
+   assign wb_clk = i_clk;
+   assign wb_rst = i_rst;
+
+   reg [27:0] cnt = 28'd0;
+   always @(posedge i_clk) cnt <= cnt + 28'd1;
+
+   assign l2 = cnt[21];
+
+   servant
+     #(.memfile (memfile),
+       .memsize (memsize))
+   servant
+     (.wb_clk (wb_clk),
+      .wb_rst (wb_rst),
+      .q      (q));
+
+endmodule