FIXME: Check

rtl/serv_ctrl.v

@@ -30,14 +30,14 @@ module serv_ctrl
    //External
    output reg [31:0] o_ibus_adr);
 
-   wire [B:1] zeroB = 0;
-
    wire [B:0] pc_plus_4;
    wire       pc_plus_4_cy;
    reg 	      pc_plus_4_cy_r;
+   wire [B:0] pc_plus_4_cy_r_w;
    wire [B:0] pc_plus_offset;
    wire       pc_plus_offset_cy;
-   reg 	      pc_plus_offset_cy_r;
+   reg	      pc_plus_offset_cy_r;
+   wire [B:0] pc_plus_offset_cy_r_w;
    wire [B:0] pc_plus_offset_aligned;
    wire [B:0] plus_4;
 
@@ -54,7 +54,7 @@ module serv_ctrl
 
    assign o_bad_pc = pc_plus_offset_aligned;
 
-   assign {pc_plus_4_cy,pc_plus_4} = pc+plus_4+{zeroB, pc_plus_4_cy_r};
+   assign {pc_plus_4_cy,pc_plus_4} = pc+plus_4+pc_plus_4_cy_r_w;
 
    generate
       if (|WITH_CSR)
@@ -66,13 +66,19 @@ module serv_ctrl
 
    assign offset_a = i_pc_rel ? pc : 0;
    assign offset_b = i_utype ? (i_cnt12to31 ? i_imm : 0) : i_buf;
-   assign {pc_plus_offset_cy,pc_plus_offset} = offset_a+offset_b+{zeroB, pc_plus_offset_cy_r};
+   assign {pc_plus_offset_cy,pc_plus_offset} = offset_a+offset_b+pc_plus_offset_cy_r_w;
 
    generate
-      if (W>1) assign pc_plus_offset_aligned[B:1] = pc_plus_offset[B:1];
+      if (W>1) begin
+	 assign pc_plus_offset_aligned[B:1] = pc_plus_offset[B:1];
+	 assign pc_plus_offset_cy_r_w[B:1] = {B{1'b0}};
+	 assign pc_plus_4_cy_r_w[B:1] = {B{1'b0}};
+      end
    endgenerate
 
    assign pc_plus_offset_aligned[0] = pc_plus_offset[0] & !i_cnt0;
+   assign pc_plus_offset_cy_r_w[0] = pc_plus_offset_cy_r;
+   assign pc_plus_4_cy_r_w[0] = pc_plus_4_cy_r;
 
    initial if (RESET_STRATEGY == "NONE") o_ibus_adr = RESET_PC;