synthesis: update constraints to be more careful about identifying re…

…set nets
nvdla · Mar 2, 2018 · eb2564c · eb2564c
1 parent 8bb3f1d
commit eb2564c
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Showing 5 changed files with 7 additions and 10 deletions.
diff --git a/syn/cons/NV_NVDLA_partition_a.sdc b/syn/cons/NV_NVDLA_partition_a.sdc
@@ -10,16 +10,15 @@
 set_max_area 0
 set_ideal_network [get_ports direct_reset_]
 set_ideal_network [get_ports dla_reset_rstn]
+set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
 set_ideal_network [get_ports test_mode]
-set_ideal_network [get_pins u_partition_a_reset/synced_rstn]    # [get_ports nvdla_core_rstn]
 create_clock [get_ports nvdla_core_clk]  -period 0.9  -waveform {0 0.45}
 set_clock_transition -min -fall 0.05 [get_clocks nvdla_core_clk]
 set_clock_transition -min -rise 0.05 [get_clocks nvdla_core_clk]
 set_clock_transition -max -fall 0.05 [get_clocks nvdla_core_clk]
 set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk]
 set_false_path   -from [get_ports direct_reset_]
 set_false_path   -from [get_ports dla_reset_rstn]
-set_false_path   -from [get_pins u_partition_a_reset/synced_rstn]    # [get_ports nvdla_core_rstn]
 set_false_path   -from [get_ports test_mode]
 set_false_path   -from [get_ports pwrbus_ram_pd*]
 set_false_path   -from [get_ports tmc2slcg_disable_clock_gating]

diff --git a/syn/cons/NV_NVDLA_partition_c.sdc b/syn/cons/NV_NVDLA_partition_c.sdc
@@ -10,16 +10,15 @@
 set_max_area 0
 set_ideal_network [get_ports direct_reset_]
 set_ideal_network [get_ports dla_reset_rstn]
+set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
 set_ideal_network [get_ports test_mode]
-set_ideal_network [get_pins u_partition_c_reset/synced_rstn]    # [get_ports nvdla_core_rstn]
 create_clock [get_ports nvdla_core_clk]  -period 0.9  -waveform {0 0.45}
 set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk]
 set_clock_transition -max -fall 0.05 [get_clocks nvdla_core_clk]
 set_clock_transition -min -rise 0.05 [get_clocks nvdla_core_clk]
 set_clock_transition -min -fall 0.05 [get_clocks nvdla_core_clk]
 set_false_path   -from [get_ports direct_reset_]
 set_false_path   -from [get_ports dla_reset_rstn]
-set_false_path   -from [get_pins u_partition_c_reset/synced_rstn]    # [get_ports nvdla_core_rstn]
 set_false_path   -from [get_ports test_mode]
 set_false_path   -from [get_ports pwrbus_ram_pd*]
 set_false_path   -from [get_ports tmc2slcg_disable_clock_gating]

diff --git a/syn/cons/NV_NVDLA_partition_m.sdc b/syn/cons/NV_NVDLA_partition_m.sdc
@@ -10,16 +10,15 @@
 set_max_area 0
 set_ideal_network [get_ports direct_reset_]
 set_ideal_network [get_ports dla_reset_rstn]
+set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
 set_ideal_network [get_ports test_mode]
-set_ideal_network [get_pins u_partition_m_reset/synced_rstn]    # [get_ports nvdla_core_rstn]
 create_clock [get_ports nvdla_core_clk]  -period 0.9  -waveform {0 0.45}
 set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk]
 set_clock_transition -max -fall 0.05 [get_clocks nvdla_core_clk]
 set_clock_transition -min -rise 0.05 [get_clocks nvdla_core_clk]
 set_clock_transition -min -fall 0.05 [get_clocks nvdla_core_clk]
 set_false_path   -from [get_ports direct_reset_]
 set_false_path   -from [get_ports dla_reset_rstn]
-set_false_path   -from [get_pins u_partition_m_reset/synced_rstn]    # [get_ports nvdla_core_rstn]
 set_false_path   -from [get_ports test_mode]
 set_false_path   -from [get_ports tmc2slcg_disable_clock_gating]
 set_false_path   -from [get_ports global_clk_ovr_on]

diff --git a/syn/cons/NV_NVDLA_partition_o.sdc b/syn/cons/NV_NVDLA_partition_o.sdc
@@ -11,7 +11,7 @@ set_max_area 0
 set_ideal_network [get_ports test_mode]
 set_ideal_network [get_ports direct_reset_]
 set_ideal_network [get_ports dla_reset_rstn]
-set_ideal_network [get_pins u_partition_o_reset/synced_rstn]    # [get_ports nvdla_core_rstn]
+set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
 create_clock [get_ports nvdla_core_clk]  -period 0.9  -waveform {0 0.45}
 set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk]
 set_clock_transition -max -fall 0.05 [get_clocks nvdla_core_clk]
@@ -24,8 +24,9 @@ set_clock_transition -min -rise 0.05 [get_clocks nvdla_falcon_clk]
 set_clock_transition -min -fall 0.05 [get_clocks nvdla_falcon_clk]
 set_false_path   -from [get_ports direct_reset_]
 set_false_path   -from [get_ports dla_reset_rstn]
-set_false_path   -from [get_pins u_partition_o_reset/synced_rstn]    # [get_ports nvdla_core_rstn]
 set_false_path   -from [get_ports test_mode]
 set_false_path   -from [get_ports pwrbus_ram_pd*]
 set_false_path   -from [get_ports tmc2slcg_disable_clock_gating]
 set_false_path   -from [get_ports global_clk_ovr_on]
+set_false_path   -from [get_clocks nvdla_core_clk] -to [get_clocks nvdla_falcon_clk]
+set_false_path   -from [get_clocks nvdla_falcon_clk] -to [get_clocks nvdla_core_clk]
diff --git a/syn/cons/NV_NVDLA_partition_p.sdc b/syn/cons/NV_NVDLA_partition_p.sdc
@@ -10,7 +10,7 @@
 set_max_area 0
 set_ideal_network [get_ports direct_reset_]
 set_ideal_network [get_ports dla_reset_rstn]
-set_ideal_network [get_pins u_partition_p_reset/synced_rstn]    # [get_ports nvdla_core_rstn]
+set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
 set_ideal_network [get_ports test_mode]
 create_clock [get_ports nvdla_core_clk]  -period 0.9  -waveform {0 0.45}
 set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk]
@@ -19,7 +19,6 @@ set_clock_transition -min -rise 0.05 [get_clocks nvdla_core_clk]
 set_clock_transition -min -fall 0.05 [get_clocks nvdla_core_clk]
 set_false_path   -from [get_ports direct_reset_]
 set_false_path   -from [get_ports dla_reset_rstn]
-set_false_path   -from [get_pins u_partition_p_reset/synced_rstn]    # [get_ports nvdla_core_rstn]
 set_false_path   -from [get_ports test_mode]
 set_false_path   -from [get_ports pwrbus_ram_pd*]
 set_false_path   -from [get_ports tmc2slcg_disable_clock_gating]