Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.
Use ncverilog
- ncverilog top_tb.sv +define+progX +access+r +sv +notimingcheck (X is 0 to 4)
-
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nietzhuang/RISC-V-SoC-Design
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Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.
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