A simple 32-bit 5-stage RISC-V processor in SystemVerilog based on the book Computer Organization and Design by Patterson & Hennesy. Inspired by https://github.com/masoud-ata/PH-RISC-V
The list of commands that are (to be) implemented:
-
Notifications
You must be signed in to change notification settings - Fork 0
A simple 32-bit 5-stage RISC-V processor in SystemVerilog based on the book Computer Organization and Design by Patterson & Hennesy. Inspired by https://github.com/masoud-ata/PH-RISC-V
License
mmzeynalli/RISC-V
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
A simple 32-bit 5-stage RISC-V processor in SystemVerilog based on the book Computer Organization and Design by Patterson & Hennesy. Inspired by https://github.com/masoud-ata/PH-RISC-V
Resources
License
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published