Provide an additional target for the compiler class project in HPC0 next semester.
It is a simple implementation of the ULM (Ulm Lecture Machine) on a iCEBreaker FPGA.
It's a working prototype, and it's is doing what it was designed for. When I
started the project it was my first encounter with Verilog and
SystemVerilog and the first time I had an FPGA in my hands. This means that
there is lots of potential for improvement. And if time permits I will do so.
If you are also a newbie you might be interested in places where you find some information on getting started:
- Project F
- Verilator introduction
- SystemVerilog tutorial
- ... I will extend and comment this list ...
