Fix STM32 I2C v2 async transfer not doing a repeated start

[multiplemonomials]

Summary of changes

Found a minor I2C issue when doing testing with the CI shield v2. When you do an I2C async transfer that is both a write and a read, it should do the write first, then a repeated start, then the read. This is worth doing for 3 reasons:

1. It's slightly more efficient in terms of data rate on the bus
2. In multi-master applications, it ensures that nothing else can use the bus between the write and the read
3. A small percentage of chips (e.g. the U-Blox MAX-8) require repeated starts and won't work without them.

However, the stm32 I2C HAL was not doing repeated starts, and instead was generating something like

Start Wr[0xa0] Ack 0x00 Ack 0x01 Ack Stop Start Rd[0xa1] Ack 0x02 Nack Stop

Now, with this patch, a single transfer call always does a repeated start:

Start Wr[0xa0] Ack 0x00 Ack 0x01 Ack RepeatedStart Rd[0xa1] Ack 0x02 Nack Stop

(this is using the Sigrok logic analyzer on the new CI shield to decode and evaluate I2C data).

Impact of changes

Async transfers containing a write and a read now do repeated starts on STM32 I2C v2 hardware.

Migration actions required

Documentation

Docs have been slightly updated to clarify that this transfer() does a repeated start.

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Pull request type

[X] Patch update (Bug fix / Target update / Docs update / Test update / Refactor)
[] Feature update (New feature / Functionality change / New API)
[] Major update (Breaking change E.g. Return code change / API behaviour change)

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Test results

[] No Tests required for this change (E.g docs only update)
[] Covered by existing mbed-os tests (Greentea or Unittest)
[X] Tests / results supplied as part of this PR

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Reviewers

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