Fix DMA getting stuck on STM32F4, F7, and F2

mbed-ce · Nov 2, 2023 · dd9989c · dd9989c
1 parent d8be1ff
commit dd9989c
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Showing 6 changed files with 53 additions and 9 deletions.
diff --git a/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/STM32F2xx_HAL_Driver/stm32f2xx_hal_dma_ex.c b/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/STM32F2xx_HAL_Driver/stm32f2xx_hal_dma_ex.c
@@ -202,7 +202,18 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_
 
     /* Enable Common interrupts*/
     hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
-    hdma->Instance->FCR |= DMA_IT_FE;
+
+    /* Mbed CE mod: Only enable the FIFO Error interrupt if the FIFO is actually enabled.
+     * If it's not enabled, then this interrupt can trigger spuriously from memory bus
+     * stalls that the DMA engine encounters, and this creates random DMA failures.
+     * Reference forum thread here:
+     * https://community.st.com/t5/stm32-mcus-products/spi-dma-fifo-error-issue-feifx/td-p/537074
+     * also: https://community.st.com/t5/stm32-mcus-touch-gfx-and-gui/spi-dma-error-is-occurred-when-the-other-dma-memory-to-memory-is/td-p/191590
+     */
+    if(hdma->Instance->FCR & DMA_SxFCR_DMDIS)
+    {
+      hdma->Instance->FCR |= DMA_IT_FE;
+    }
 
     if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
     {

diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma_ex.c
@@ -202,7 +202,18 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_
 
     /* Enable Common interrupts*/
     hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
-    hdma->Instance->FCR |= DMA_IT_FE;
+
+    /* Mbed CE mod: Only enable the FIFO Error interrupt if the FIFO is actually enabled.
+     * If it's not enabled, then this interrupt can trigger spuriously from memory bus
+     * stalls that the DMA engine encounters, and this creates random DMA failures.
+     * Reference forum thread here:
+     * https://community.st.com/t5/stm32-mcus-products/spi-dma-fifo-error-issue-feifx/td-p/537074
+     * also: https://community.st.com/t5/stm32-mcus-touch-gfx-and-gui/spi-dma-error-is-occurred-when-the-other-dma-memory-to-memory-is/td-p/191590
+     */
+    if(hdma->Instance->FCR & DMA_SxFCR_DMDIS)
+    {
+      hdma->Instance->FCR |= DMA_IT_FE;
+    }
 
     if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
     {

diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma.c
@@ -479,8 +479,19 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
 
     /* Enable Common interrupts*/
     hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
-    hdma->Instance->FCR |= DMA_IT_FE;
-
+
+    /* Mbed CE mod: Only enable the FIFO Error interrupt if the FIFO is actually enabled.
+     * If it's not enabled, then this interrupt can trigger spuriously from memory bus
+     * stalls that the DMA engine encounters, and this creates random DMA failures.
+     * Reference forum thread here:
+     * https://community.st.com/t5/stm32-mcus-products/spi-dma-fifo-error-issue-feifx/td-p/537074
+     * also: https://community.st.com/t5/stm32-mcus-touch-gfx-and-gui/spi-dma-error-is-occurred-when-the-other-dma-memory-to-memory-is/td-p/191590
+     */
+    if(hdma->Instance->FCR & DMA_SxFCR_DMDIS)
+    {
+      hdma->Instance->FCR |= DMA_IT_FE;
+    }
+
     if(hdma->XferHalfCpltCallback != NULL)
     {
       hdma->Instance->CR  |= DMA_IT_HT;

diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma_ex.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma_ex.c
@@ -197,7 +197,18 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_
 
     /* Enable Common interrupts*/
     hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
-    hdma->Instance->FCR |= DMA_IT_FE;
+
+    /* Mbed CE mod: Only enable the FIFO Error interrupt if the FIFO is actually enabled.
+     * If it's not enabled, then this interrupt can trigger spuriously from memory bus
+     * stalls that the DMA engine encounters, and this creates random DMA failures.
+     * Reference forum thread here:
+     * https://community.st.com/t5/stm32-mcus-products/spi-dma-fifo-error-issue-feifx/td-p/537074
+     * also: https://community.st.com/t5/stm32-mcus-touch-gfx-and-gui/spi-dma-error-is-occurred-when-the-other-dma-memory-to-memory-is/td-p/191590
+     */
+    if(hdma->Instance->FCR & DMA_SxFCR_DMDIS)
+    {
+      hdma->Instance->FCR |= DMA_IT_FE;
+    }
 
     if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
     {

diff --git a/targets/TARGET_STM/stm_dma_utils.h b/targets/TARGET_STM/stm_dma_utils.h
@@ -26,11 +26,11 @@
 
 // determine DMA IP version using the available constants in the chip header
 #if defined(GPDMA1)
-#define DMA_IP_VERSION_V3
+#define DMA_IP_VERSION_V3 1
 #elif defined(DMA1_Channel1)
-#define DMA_IP_VERSION_V2
+#define DMA_IP_VERSION_V2 1
 #else
-#define DMA_IP_VERSION_V1
+#define DMA_IP_VERSION_V1 1
 #endif
 
 // Include correct header for the IP version

diff --git a/tools/cmake/mbed-run-greentea-test.in.cmake b/tools/cmake/mbed-run-greentea-test.in.cmake
@@ -14,7 +14,7 @@ set(MBEDHTRUN_ARGS --skip-flashing @MBED_HTRUN_ARGUMENTS@) # filled in by config
 
 # Print out command
 string(REPLACE ";" " " MBEDHTRUN_ARGS_FOR_DISPLAY "${MBEDHTRUN_ARGS}")
-message("Executing: mbedhtrun ${MBEDHTRUN_ARGS_FOR_DISPLAY}")
+message("Executing: @Python3_EXECUTABLE@ -m mbed_host_tests.mbedhtrun ${MBEDHTRUN_ARGS_FOR_DISPLAY}")
 
 # Note: For this command, we need to survive mbedhtrun not being on the PATH, so we import the package and call the main function using "python -c"
 execute_process(