Merge remote-tracking branch 'origin/master' into custom_upload_method

connectivity/mbedtls/tests/TESTS/mbedtls/selftest/CMakeLists.txt

@@ -1,6 +1,10 @@
 # Copyright (c) 2021 ARM Limited. All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
+if(NOT "DEVICE_TRNG=1" IN_LIST MBED_TARGET_DEFINITIONS)
+    set(TEST_SKIPPED "This test requires TRNG support!")
+endif()
+
 if(MBED_GREENTEA_TEST_BAREMETAL)
     set(TEST_SKIPPED "This test requires an RTOS!")
 endif()

connectivity/netsocket/tests/TESTS/netsocket/tls/CMakeLists.txt

@@ -27,6 +27,10 @@ if(MBED_GREENTEA_TEST_BAREMETAL)
     set(TEST_SKIPPED "This test requires an RTOS!")
 endif()
 
+if(NOT "DEVICE_TRNG=1" IN_LIST MBED_TARGET_DEFINITIONS)
+    set(TEST_SKIPPED "This test requires TRNG support!")
+endif()
+
 mbed_greentea_add_test(
     TEST_NAME
         mbed-connectivity-netsocket-tls

drivers/device_key/tests/TESTS/device_key/functionality/CMakeLists.txt

@@ -5,7 +5,7 @@ if(NOT "DEVICE_TRNG=1" IN_LIST MBED_TARGET_DEFINITIONS)
 	set(TEST_SKIPPED "True RNG is not supported for this target so device key cannot be used")
 endif()
 
-if(NOT "DEVICE_FLASH=1" IN_LIST MBED_TARGET_DEFINITIONS)
+if(NOT ("DEVICE_FLASH=1" IN_LIST MBED_TARGET_DEFINITIONS AND "COMPONENT_FLASHIAP=1" IN_LIST MBED_TARGET_DEFINITIONS))
 	set(TEST_SKIPPED "Flash IAP is not supported for this target so device key cannot be used")
 endif()
 

drivers/usb/tests/TESTS/usb_device/README.md

@@ -29,25 +29,11 @@ See also [Known issues](#known-issues).
     1. Plug both USB interfaces (*DAPLink* and *USB device*).
 
 ### Linux
-1. Install the `hidapi` Python module, otherwise some USB HID test cases will
-    be skipped. This module is not installed during the initial setup due to
-    external dependencies for Linux.
-
-    For Debian-based Linux distros, the dependencies can be installed as follows
-    (based on module's [README][LN-hidapi_readme]):
-
-    ```bash
-    apt-get install python-dev libusb-1.0-0-dev libudev-dev
-    pip install --upgrade setuptools
-    ```
-
-    To install the `hidapi` module itself, please use the attached
-    [requirements.txt][LN-hid_requirements] file:
-
-    ```bash
-    pip install -r TESTS/usb_device/hid/requirements.txt
-    ```
-2. Add your user to the `plugdev` group with `sudo usermod -G plugdev <your username>`
+1. Install the `hidapi` and `usb` (aka pyusb) Python modules.  It's recommended to install these via a package manager because they have some binary dependencies:
+```
+sudo apt-get install python3-hidapi python3-usb
+```
+2. Add your user to the `plugdev` group with `sudo usermod -a -G plugdev <your username>`
 3. Update the `udev` rules for the USB VIDs/PIDs used in the test as follows:
 
     ```bash
@@ -67,6 +53,22 @@ See also [Known issues](#known-issues).
     port and sending the `AT commands`, which it does for every new
     `/dev/ttyACM` device registered in system.
 4. Install the `udisks2` package, which the test script uses to mount USB disks.  Additionally, you may need to disable any automounting of disks provided by your file manager / distro.
+5. Last but not least, at least on Ubuntu, you may need to change permission settings such that udisks2 actually allows ordinary users to mount disks.  You are supposed to do this with a [polkit rule](https://askubuntu.com/a/1457819/1612342), but I had absolutely no luck getting this to work.  So instead I had to edit `/usr/share/polkit-1/actions/org.freedesktop.UDisks2.policy1` and change the first
+```
+    <defaults>
+      <allow_any>auth_admin</allow_any>
+      <allow_inactive>auth_admin</allow_inactive>
+      <allow_active>yes</allow_active>
+    </defaults>
+```
+block to
+```
+    <defaults>
+      <allow_any>yes</allow_any>
+      <allow_inactive>yes</allow_inactive>
+      <allow_active>yes</allow_active>
+    </defaults>
+```
 
 ### Mac
 No setup method has been verified for this platform.

targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_ARM/LPC1768.ld

@@ -135,7 +135,7 @@ SECTIONS
     } > RAM
 
 
-    .bss :
+    .bss (NOLOAD):
     {
         __bss_start__ = .;
         *(.bss*)
@@ -145,7 +145,7 @@ SECTIONS
     } > RAM
 
 
-    .heap :
+    .heap (NOLOAD):
     {
         __end__ = .;
         end = __end__;
@@ -157,7 +157,7 @@ SECTIONS
     /* .stack_dummy section doesn't contains any symbols. It is only
      * used for linker to calculate size of stack sections, and assign
      * values to stack symbols later */
-    .stack_dummy :
+    .stack_dummy (NOLOAD):
     {
         *(.stack)
     } > RAM

targets/upload_method_cfg/LPC1768.cmake

@@ -32,7 +32,4 @@ set(MBED_RESET_BAUDRATE 115200)
 
 set(OPENOCD_UPLOAD_ENABLED TRUE)
 set(OPENOCD_CHIP_CONFIG_COMMANDS
-    -f ${CMAKE_CURRENT_LIST_DIR}/openocd_cfgs/lpc1768.cfg
-    -c "gdb_memory_map disable" # prevents OpenOCD crash on GDB connect
-	-c "gdb_breakpoint_override hard" # Make sure GDB uses HW breakpoints
-    )
+    -f ${CMAKE_CURRENT_LIST_DIR}/openocd_cfgs/lpc1768.cfg)

targets/upload_method_cfg/openocd_cfgs/lpc1768.cfg

@@ -1,5 +1,197 @@
 source [find interface/cmsis-dap.cfg]
-source [find target/lpc17xx.cfg]
+
+# The below contents are is copied from the OpenOCD scripts for the lpc1768 with only *one* change:
+# the "flash bank" line has been commented out so that we can configure the bank manually.
+# I wasn't able to find a way to use the lpc17xx.cfg include file and not have it run this line.
+# Original sources:
+# - https://github.com/openocd-org/openocd/blob/master/tcl/target/lpc17xx.cfg
+# - https://github.com/openocd-org/openocd/blob/master/tcl/target/lpc1xxx.cfg
+
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP LPC17xx Cortex-M3 with at least 8kB SRAM
+set CHIPNAME lpc17xx
+set CHIPSERIES lpc1700
+if { ![info exists WORKAREASIZE] } {
+	set WORKAREASIZE 0x2000
+}
+
+# Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts
+#
+# !!!!!!
+#
+# This file should not be included directly, rather by the lpc11xx.cfg,
+# lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the
+# appropriate values.
+#
+# !!!!!!
+
+# LPC8xx chips support only SWD transport.
+# LPC11xx chips support only SWD transport.
+# LPC12xx chips support only SWD transport.
+# LPC11Uxx chips support only SWD transports.
+# LPC13xx chips support only SWD transports.
+# LPC17xx chips support both JTAG and SWD transports.
+# LPC40xx chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
+}
+
+if { [info exists CHIPSERIES] } {
+	# Validate chip series is supported
+	if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700"  && $CHIPSERIES != "lpc4000" } {
+		error "Unsupported LPC1xxx chip series specified."
+	}
+	set _CHIPSERIES $CHIPSERIES
+} else {
+	error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
+}
+
+# After reset, the chip is clocked by an internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+# CCLK is the core clock frequency in KHz
+if { [info exists CCLK] } {
+	# Allow user override
+	set _CCLK $CCLK
+} else {
+	# LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x)
+	if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
+		set _CCLK 12000
+	} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
+		set _CCLK 4000
+	}
+}
+
+if { [info exists CPUTAPID] } {
+	# Allow user override
+	set _CPUTAPID $CPUTAPID
+} else {
+	# LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core.
+	if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
+		set _CPUTAPID 0x0bb11477
+	} elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
+		if { [using_jtag] } {
+			set _CPUTAPID 0x4ba00477
+		} {
+			set _CPUTAPID 0x2ba01477
+		}
+	}
+}
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	error "WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE."
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000)
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
+
+# The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
+# The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000)
+# The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000)
+# The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)
+# The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)
+# The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000)
+#
+# All are compatible with the "lpc1700" variant of the LPC2000 flash driver
+# (same cmd51 destination boundary alignment, and all three support 256 byte
+# transfers).
+#
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] [iap entry]
+set _IAP_ENTRY 0
+if { [info exists IAP_ENTRY] } {
+	set _IAP_ENTRY $IAP_ENTRY
+}
+set _FLASHNAME $_CHIPNAME.flash
+#flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \
+#	lpc1700 $_CCLK calc_checksum $_IAP_ENTRY
+
+if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
+	# Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
+	# "User Flash Mode" where interrupt vectors are _not_ remapped,
+	# and reside in flash instead).
+	#
+	# Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
+	# Bit Symbol Value Description
+	# 1:0 MAP          System memory remap
+	#            0x0   Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
+	#            0x1   User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
+	#            0x2   User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
+	# 31:2 -     -     Reserved.
+	$_TARGETNAME configure -event reset-init {
+		mww 0x40048000 0x02
+	}
+} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
+	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
+	# "User Flash Mode" where interrupt vectors are _not_ remapped,
+	# and reside in flash instead).
+	#
+	# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
+	# Bit Symbol Value Description Reset
+	# value
+	# 0 MAP Memory map control. 0
+	# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
+	# 1 User mode. The on-chip Flash memory is mapped to address 0.
+	# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
+	#
+	# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
+	$_TARGETNAME configure -event reset-init {
+		mww 0x400FC040 0x01
+	}
+}
+
+# Run with *real slow* clock by default since the
+# boot rom could have been playing with the PLL, so
+# we have no idea what clock the target is running at.
+adapter speed 10
+
+# delays on reset lines
+adapter srst delay 200
+if {[using_jtag]} {
+ jtag_ntrst_delay 200
+}
+
+# LPC8xx (Cortex-M0+ core) support SYSRESETREQ
+# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ
+# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ
+# LPC40xx (Cortex-M4F core) support SYSRESETREQ
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+
+# It seems like there's some sort of issue with the OpenOCD memory auto-probing for this part.
+# When connecting, you often (though not always) get:
+#
+# Debug: 265 9395 lpc2000.c:850 lpc2000_iap_call(): IAP command = 54 (0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000) completed with result = 0737212c
+# Debug: 266 9395 target.c:2143 target_free_working_area_restore(): freed 260 bytes of working area at address 0x10000000
+# Debug: 267 9395 target.c:1940 print_wa_layout():    0x10000000-0x10001fff (8192 bytes)
+# Error: 268 9395 lpc2000.c:1513 lpc2000_auto_probe_flash(): BUG: unknown Part ID encountered: 0xaaa0
+#
+# We can avoid this by manually configuring the flash driver instead of using autoprobing.
+flash bank $_FLASHNAME lpc2000 0x0 0x00080000 0 0 $_TARGETNAME lpc1700 $_CCLK calc_checksum $_IAP_ENTRY
 
 # For some reason, the bundled OpenOCD LPC1768 scripts set a _very_ slow default speed that makes programming
 # take several minutes.  Increasing it seems to work OK.

tools/cmake/mbed_greentea.cmake

@@ -113,7 +113,11 @@ function(mbed_greentea_add_test)
 
     # All of the upload methods already reset the chip after uploading so we don't need to reset via
     # the serial port.  Doing that type of reset also seems to give the Pitaya-Link probe trouble.
-    list(APPEND MBED_HTRUN_ARGUMENTS --skip-reset)
+    # However, for targets which support semihosting (currently just LPC1768), we do need the reset as otherwise
+    # semihosting stuff like localfilesystem won't work.
+    if(NOT "DEVICE_SEMIHOST=1" IN_LIST MBED_TARGET_DEFINITIONS)
+        list(APPEND MBED_HTRUN_ARGUMENTS --skip-reset)
+    endif()
 
     if(DEFINED MBED_GREENTEA_EXTRA_HTRUN_ARGUMENTS)
         list(APPEND MBED_HTRUN_ARGUMENTS ${MBED_GREENTEA_EXTRA_HTRUN_ARGUMENTS})

tools/cmake/upload_methods/UploadMethodJLINK.cmake

@@ -98,7 +98,7 @@ set(UPLOAD_LAUNCH_COMMANDS
 	"monitor halt"
 	"monitor reset"
 	"load"
-	"break main"
+	"tbreak main"
 	"monitor reset"
 )
 set(UPLOAD_RESTART_COMMANDS

tools/cmake/upload_methods/UploadMethodOPENOCD.cmake

@@ -47,6 +47,7 @@ function(gen_upload_target TARGET_NAME BIN_FILE)
 		COMMAND ${OpenOCD}
 		${OPENOCD_CHIP_CONFIG_COMMANDS}
 		${OPENOCD_ADAPTER_SERIAL_COMMAND}
+		-c "gdb_port disabled" # Don't start a GDB server when just programming
 		-c "program $<TARGET_FILE:${TARGET_NAME}> reset exit"
 		VERBATIM)
 
@@ -69,8 +70,17 @@ set(UPLOAD_WANTS_EXTENDED_REMOTE TRUE)
 # Reference: https://github.com/Marus/cortex-debug/blob/056c03f01e008828e6527c571ef5c9adaf64083f/src/openocd.ts#L100
 set(UPLOAD_LAUNCH_COMMANDS
 	"monitor reset halt"
+
+	# For targets which support semihosting, prevent GDB from stopping when a semihosting event happens.
+	# AFAIK, semihosting is only used to communicate between the interface chip and the CPU; we never
+	# want to process semihosting data on the host
+	"handle SIGTRAP nostop noprint"
+
+	# Increase remote timeout to 30 sec in case programming takes a long time
+	"set remotetimeout 30"
+
 	"load"
-	"break main"
+	"tbreak main"
 	"monitor reset halt"
 )
 set(UPLOAD_RESTART_COMMANDS

tools/cmake/upload_methods/UploadMethodPYOCD.cmake

@@ -56,7 +56,7 @@ set(UPLOAD_GDBSERVER_DEBUG_COMMAND
 set(UPLOAD_LAUNCH_COMMANDS
 "monitor reset halt"
 "load"
-"break main"
+"tbreak main"
 )
 set(UPLOAD_RESTART_COMMANDS
 "monitor reset"

tools/cmake/upload_methods/UploadMethodSTLINK.cmake

@@ -50,7 +50,7 @@ set(UPLOAD_LAUNCH_COMMANDS
 	"monitor halt"
 	"monitor reset"
 	"load"
-	"break main"
+	"tbreak main"
 	"monitor reset"
 )
 set(UPLOAD_RESTART_COMMANDS

tools/cmake/upload_methods/UploadMethodSTM32CUBE.cmake

@@ -61,7 +61,7 @@ set(UPLOAD_GDBSERVER_DEBUG_COMMAND
 set(UPLOAD_LAUNCH_COMMANDS
 	"monitor reset"
 	"load"
-	"break main"
+	"tbreak main"
 	"monitor reset"
 )
 set(UPLOAD_RESTART_COMMANDS

tools/requirements-ci-build.apt.txt

@@ -0,0 +1,3 @@
+python3-usb
+python3-hidapi
+udisks2