Update chiselVersion to v6.6.0 #22
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This PR contains the following updates:
6.2.0->6.6.06.2.0->6.6.0Release Notes
chipsalliance/chisel (org.chipsalliance:chisel)
v6.6.0: Chisel v6.6.0Compare Source
Features
When trying to drill a port, it doesn't matter if the module is closed. We do not need to construct new hardware and can just use the existing port.
API Modification
API Deprecation
Fixes
This fixes an issue with views of List of Property.
This ensures boring from an OpaqueType that wraps a Property uses the correct connection operator in the IR.
BoringUtils.rwTap can now works on a port of an
instance: Instance[..]Probe chisel types now include the kind of probe and layer in their
.toStringmethodDocumentation
Dependency Updates
Add support for Scala 2.13.15
Build and Internal Changes
Full Changelog: chipsalliance/chisel@v6.5.0...v6.6.0
v6.5.0: Chisel v6.5.0Compare Source
Features
SimulationData.expectcalls now record source location and report it in theFailedExpectationExceptionon failure.This is mostly useful for initial values for async reset registers and for constructing literal values in testing contexts (e.g. ChiselSim). It also should slightly reduce memory use and
.firsize.Users can call
.readOnlyon anyDatato prevent connections to the returned value. Resolves https://github.com/chipsalliance/chisel/issues/1267.Emits a file without returning the serialized object which is more memory efficient and supports > 2 GiB of serialized FIRRTL text.
Make Add a contextual message to Data.requireTypeEquivalent and expose a public API in DataMirror.requireTypeEquivalent, to make it easier for user code to have good error messages when requiring type equivalence between two chisel Datas
Users can now apply a function
fto thebitsfield of aValidinstance with the newValid.map(f)method.Add more information to the error message when attempting to
probe.defineto a mismatched chisel type.API Deprecation
Previously,
.asTypeOfwould return aWire. To get the old behavior, wrap the.asTypeOfcall inWireInit(...).Performance
This reduces memory use by
n - 1times 16-bytes for an Aggregate withnelements.This reduces memory use of a typical bundle by 20%.
This reduces memory use by n - 1 times 16-bytes for an Aggregate with n elements.
This saves 16-bytes per Vec element.
Fixes
This makes
.toStringbehavior better outside of Chisel elaboration contexts.This is already an error caught in firtool, now Chisel will error earlier.
Fixes #4185, Fixes #4187
Previously, VecInit would try to "intelligently" select := or <> depending on if the type is bidirectional. :<>= has the desirable behavior here for both passive and bidirectional types. It also has the advantage over <> of handling internal wires.
Documentation
Build and Internal Changes
Full Changelog: chipsalliance/chisel@v6.4.0...v6.5.0
v6.4.0: Chisel v6.4.0Compare Source
Features
Added
modulePortsandfullModulePortsmethods inDataMirrorthat returns all ports on anInstanceof a module.API Modification
Now checkTypeEquivalence will check whether data have the same probe type modifier including writeability and color (layer).
API Deprecation
It should never have been a public API.
Fixes
Fix Nested Instantiate
Previously, a view of an empty aggregate would incorrectly always have a litValue of
0.Fix muxing and probing of views of Aggregates
AssertPropertyfailing to fire in verilator simulation.Previously, the user-specified (or unspecified minimum width) of the literal would be used in some operations like concatenation. For literal values that are too-wide, they will now truncate to the correct width. This will become a warning (then later an error) in newer major versions of Chisel.
Always return fully aligned result from tapAndRead, even if no boring performed.
Fix tapping mix-alignment signal from parent.
Fix failing ChiselSim/SVsim error to simulate modules with zero-width ports.
Also fix reifySingleData to return the Data itself if it is not a view.
Fix for #4102. Now supported are FlatIO (and therefore FixedIO___Module) of:
Dependency Updates
Build and Internal Changes
Added a unit test for FlatIO Ordering being maintained
Full Changelog: chipsalliance/chisel@v6.3.0...v6.4.0
v6.3.0: Chisel v6.3.0Compare Source
Features
Sometimes a generator wants to emit a Path that targets some Data, but that Data isn't always produced by the generator. The DeletedPath can be used to represent the presence of a Path, but the absence of a Data in this case.
This gives much better error messages when accidentally dontTouching a literal
Performance
Speeds up conversion of UInt literals to BitPat by ~9x in practice, ~70x for large UInts.
Fixes
Fixes
DataMirror.checkTypeEquivalenceto actually check all fields of Bundles and Records. This may expose latent bugs in user code.View of literals will now themselves be literals. This also fixes an internal bug related to views of literals.
Previously, the function would infinitely recurse resulting in a stack overflow.
Fixes #4007
Documentation
Existing links to
https://github.com/chipsalliance/chisel/releases/latest/download/chisel-template.scalashould instead usehttps://github.com/chipsalliance/chisel/releases/latest/download/chisel-example.scalaBuild and Internal Changes
Full Changelog: chipsalliance/chisel@v6.2.0...v6.3.0
Configuration
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