Fixed DSLX issues

masc-ucsc · Nov 18, 2024 · bd2321e · bd2321e
1 parent 8fa23b3
commit bd2321e
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Showing 2 changed files with 32 additions and 14 deletions.
diff --git a/hdlagent/agent.py b/hdlagent/agent.py
@@ -952,7 +952,7 @@ def get_verilog_file_name(original_file_name):
         elif '.pyrtl' in file_name_str:
             return file_name_str.replace('.pyrtl', '.v')
         elif '.x' in file_name_str:
-            return file_name_str.replace('.dslx', '.v')
+            return file_name_str.replace('.x', '.v')
         else:
             return file_name_str
 
@@ -1211,7 +1211,8 @@ def lec_loop(self, prompt: str, compiled: bool = False, lec_iterations: int = 1,
         for i in range(lec_iterations):
             if update and len(self.compile_conversation) == 0:
                 if self.test_code_compile() is None:
-                    self.verilog = self.code  # Ensure self.verilog is set
+                    # self.verilog = self.code  # Ensure self.verilog is set
+                    self.verilog = Agent.get_verilog_file_name(self.code)
                     gold, gate = self.reformat_verilog(self.name, self.gold, self.verilog, self.io)
                     lec_out = self.test_lec(gold, gate, lec_feedback_limit)
                     print("LEC is done Now in update!!!!!!")
@@ -1227,7 +1228,8 @@ def lec_loop(self, prompt: str, compiled: bool = False, lec_iterations: int = 1,
                         print("[DEBUG] LEC passed during update.")
                         return self.finish_run()
 
-            self.verilog = self.code  # Ensure self.verilog is set
+            # self.verilog = self.code  # Ensure self.verilog is set
+            self.verilog = Agent.get_verilog_file_name(self.code)
             gold, gate = self.reformat_verilog(self.name, self.gold, self.verilog, self.io)
             lec_out = self.test_lec(gold, gate, lec_feedback_limit)
             print("LEC is done Now!!!!!!")

diff --git a/hdlagent/resources/DSLX/DSLX_agent.py b/hdlagent/resources/DSLX/DSLX_agent.py
@@ -10,6 +10,12 @@ def custom_reformat_verilog(name: str, ref_file: str, in_file: str, io_list):
     outputs = []
     inputs  = []
 
+    print(f"[DEBUG] custom_reformat_verilog called with:")
+    print(f"        name: {name}")
+    print(f"        ref_file: {ref_file}")
+    print(f"        in_file: {in_file}")
+    print(f"        io_list: {io_list}")
+
     for io in io_list:
         #print(io)
         if io[0] == "output":
@@ -30,19 +36,29 @@ def custom_reformat_verilog(name: str, ref_file: str, in_file: str, io_list):
     #    if input_name != in_file_input_name:
     #        in_file_content = in_file_content.replace()
 
+    # Debug: Show original content
+    print(f"[DEBUG] Original Verilog content:\n{in_file_content}\n{'-'*50}")
+
     if len(outputs) == 1:
         output_name = outputs[0][3]
-        # Rename all lines that may have the output_name as a local wire
-        in_file_content = in_file_content.replace(f"{output_name}\n", f"{output_name}_w\n")
-        in_file_content = in_file_content.replace(f"{output_name};", f"{output_name}_w;")
-        in_file_content = in_file_content.replace("{" + output_name + "};", "{" + output_name + "_w};")
-        in_file_content = in_file_content.replace(f" {output_name} ", f" {output_name}_w ")
-        in_file_content = in_file_content.replace(f"({output_name});", f"({output_name}_w);")
-        # Rename output as desired output_name
-        in_file_content = in_file_content.replace("out\n", output_name + "\n")
-        in_file_content = in_file_content.replace("out;", output_name + ";")
-        in_file_content = in_file_content.replace(" out ", " " + output_name + " ")
-        in_file_content = in_file_content.replace("(out);", "(" + output_name + ");")
+        # Rename internal wires that might conflict with the output name
+        in_file_content = in_file_content.replace(f'wire [63:0] {output_name};', f'wire [63:0] {output_name}_w;')
+        in_file_content = in_file_content.replace(f'assign {output_name} =', f'assign {output_name}_w =')
+        # Replace 'out' with the correct output name
+        pattern = r'\bout\b'
+        in_file_content = re.sub(pattern, output_name, in_file_content)
+
+        # # Rename all lines that may have the output_name as a local wire
+        # in_file_content = in_file_content.replace(f"{output_name}\n", f"{output_name}_w\n")
+        # in_file_content = in_file_content.replace(f"{output_name};", f"{output_name}_w;")
+        # in_file_content = in_file_content.replace("{" + output_name + "};", "{" + output_name + "_w};")
+        # in_file_content = in_file_content.replace(f" {output_name} ", f" {output_name}_w ")
+        # in_file_content = in_file_content.replace(f"({output_name});", f"({output_name}_w);")
+        # # Rename output as desired output_name
+        # in_file_content = in_file_content.replace("out\n", output_name + "\n")
+        # in_file_content = in_file_content.replace("out;", output_name + ";")
+        # in_file_content = in_file_content.replace(" out ", " " + output_name + " ")
+        # in_file_content = in_file_content.replace("(out);", "(" + output_name + ");")
     else:
         # Replace modules header 'out' with outputs directly
         output_declarations = ""