OpenFASoC

OpenFASoC: Fully Open-Source Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits

OpenFASOC is focused on open-source automate analog generation from user specification to GDSII with fully open-sourced tools. This project is led by a team of researchers at the University of Michigan is inspired from FASoC whcih sits on proprietary tools. (See more about FaSoC at website)

Prerequisites

Please install the following tools with the recommended commit ids for a stable functioning of the flow:

1. Magic (version:8.3.320)

2. Netgen (version:1.5.227)

3. Klayout (version:0.27.10-1)

   • Please use this command to build preferably: ./build.sh -option '-j8' -noruby -without-qt-multimedia -without-qt-xml -without-qt-svg

4. Yosys (version:0.20+70)

5. OpenROAD (version:2.0_4865)

6. Open_pdks (version:1.0.328)

• open_pdks is required to run drc/lvs check and the simulations
• After open_pdks is installed, please update the open_pdks key in common/platform_config.json with the installed path, down to the sky130A folder

Other notice:

• Python 3.7 is used in this generator.
• All the required tools need to be loaded into the environment before running this generator.

Design Generation

Generators

Temperature Sensor (temp-sense-gen) - link

A fully automated SoC generator that uses an all-digital temperature sensor architecture, that relies on a new subthreshold oscillator (achieved using the auxiliary cell “Header Cell“) for realizing synthesizable thermal sensors.

Block Architecture:

• Temperature-sensitive ring oscillator and stacked zero-VT devices.

LDO Generator (ldo-gen) - link

The main idea behind a Digital LDO is the use of an array of small power transistors that operate as switches. The use of power transistors as switches facilitates low VDD power management and process scalability which makes Digital LDOs a good potential candidate for power management as we go to lower nodes. With the “Unit Power Switch” as the auxiliary cell, an automatic LDO design tool “LDO_GEN” is developed as part of this project.

Block Architecture:

• Synchronous Digital LDO with optional stochastic flash ADC.

DC-DC Generator (dcdc-gen) - link

For synthesizable on-chip power management circuits, we use the “2:1 SC Cell” auxiliary cell for implementing a switched-capacitor (SC) based DC-DC converter. By varying the number of auxiliary cells, we can achieve a wide range of conversion ratios with fine-grain resolution. It operates similarly to a successive approximation analog to digital converter (SAR ADC). Furthermore, since the total structure is simply composed of auxiliary cells, it is ideal for the proposed flow of automating the analog block design.

Cryo Generator (cryo-gen) - link

GDS Factory (gdsfactory) - link

LC-DCO Generator (lc-dco) - link

SCPA Generator (cpa-gen) - link

Our fully open-source flow only supports the temperature sensor generation so far. We are working on adding additional generators in the near future.

The generators are located inside openfasoc/generators/, the target for temperature sensor generation is sky130hd_temp and located inside openfasoc/generators/temp-sense-gen, the following parameters are supported:

• --specfile: input specifications where the min/max temperature for the temp sensor are specified
• --outputDir: output folder where the gds/def results will be exported
• --platform: only sky130hd platform is supported for now
• --clean: clean flow folder and start a fresh design flow
• --mode: support verilog/macro/full modes, macro mode runs through APR/DRC/LVS steps to generate macros, full mode completes macro generation + simulations
• --nhead: specify a fixed number of headers (optional)
• --ninv: specify a fixed number of inverters (optional)

Look more into "getting-started" section on how to run the OpenFASOC flow

Spice Simulation Flow

To run the simulation, please edit your local model file in common/platform_config.json:

• simTool: simulation tool, only ngspice is supported for now -- We plan to support Xyce in the future
• simMode: partial (recommended to reduce runtime) or full, partial simulation only includes headers and cells in low voltage domain to calculate the frequency errors, full simulation includes the internal counter (full simulation is slow using ngspice and is still being tested)
• nominal_voltage: the nominal voltage of the specified technology, it is used to set a supply voltage in the simulation testbench
• model_file: the path to the top model lib file
• model_corner: the corner used in the simulation
• an example of the common/platform_config.json looks like:

{
  "simTool": "ngspice",
  "simMode": "partial",
  "platforms": {
    "sky130hd": {
      "nominal_voltage": 1.8,
      "model_file": "~/open_pdks/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice",
      "model_corner": "tt"
    }
  }
}

Tapeouts and testing setup

Please refer to our testing setup in our tapeouts and testing setup section.

Citation

If you find this tool useful in your research, we kindly request to cite our papers:

• Tutu Ajayi et al., "An Open-source Framework for Autonomous SoC Design with Analog Block Generation," 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), 2020, pp. 141-146.
• Qirui Zhang et al., "An Open-Source and Autonomous Temperature Sensor Generator Verified With 64 Instances in SkyWater 130 nm for Comprehensive Design Space Exploration," in IEEE Solid-State Circuits Letters, vol. 5, pp. 174-177, 2022.