Merge branch 'devel'

lnls-dig · Oct 22, 2021 · bd01d1f · bd01d1f
2 parents b9a807c + cab05a3
commit bd01d1f
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Showing 18 changed files with 383 additions and 346 deletions.
diff --git a/hdl/modules/fofb_ctrl_pkg.vhd b/hdl/modules/fofb_ctrl_pkg.vhd
@@ -505,7 +505,6 @@ package fofb_ctrl_pkg is
   generic
   (
     -- Standard parameters of generic_dpram
-    g_DATA_WIDTH                               : natural := 32;
     g_SIZE                                     : natural := 512;
     g_WITH_BYTE_ENABLE                         : boolean := false;
     g_ADDR_CONFLICT_RESOLUTION                 : string  := "read_first";
@@ -531,6 +530,9 @@ package fofb_ctrl_pkg is
     -- Fixed point representation for output
     g_OUT_FIXED                                : natural := 26;
 
+    -- Extra bits for accumulator
+    g_EXTRA_WIDTH                              : natural := 4;
+
     -- Number of channels
     g_CHANNELS                                 : natural := 8;
 
@@ -586,7 +588,6 @@ package fofb_ctrl_pkg is
   generic
   (
     -- Standard parameters of generic_dpram
-    g_DATA_WIDTH                               : natural := 32;
     g_SIZE                                     : natural := 512;
     g_WITH_BYTE_ENABLE                         : boolean := false;
     g_ADDR_CONFLICT_RESOLUTION                 : string  := "read_first";
@@ -612,6 +613,9 @@ package fofb_ctrl_pkg is
     -- Fixed point representation for output
     g_OUT_FIXED                                : natural := 26;
 
+    -- Extra bits for accumulator
+    g_EXTRA_WIDTH                              : natural := 4;
+
     -- Number of channels
     g_CHANNELS                                 : natural := 8;
 

diff --git a/hdl/modules/fofb_processing/Manifest.py b/hdl/modules/fofb_processing/Manifest.py
@@ -3,7 +3,7 @@
 	"dot_prod_coeff_vec.vhd",
 	"dot_prod.vhd",
 	"dot_prod_pkg.vhd",
-	"cheby/dot_prod_wb.vhd",
+	"cheby/wb_fofb_processing_regs.vhd",
 	"wb_fofb_processing.vhd",
 	"xwb_fofb_processing.vhd"
 ];

diff --git a/hdl/modules/fofb_processing/cheby/build_cheby.sh b/hdl/modules/fofb_processing/cheby/build_cheby.sh
@@ -1,3 +1,3 @@
 #!/bin/bash
 
-cheby -i dot_prod_wb.cheby --hdl vhdl --gen-wbgen-hdl dot_prod_wb.vhd --doc html --gen-doc doc/dot_prod_wb.html --gen-c dot_prod_wb.h --consts-style verilog --gen-consts ../../../sim/regs/dot_prod_wb.vh
+cheby -i wb_fofb_processing_regs.cheby --hdl vhdl --gen-wbgen-hdl wb_fofb_processing_regs.vhd --gen-c wb_fofb_processing_regs.h --consts-style verilog --gen-consts ../../../sim/regs/wb_fofb_processing_regs.vh
diff --git a/hdl/modules/fofb_processing/cheby/dot_prod_wb.h b/hdl/modules/fofb_processing/cheby/dot_prod_wb.h
diff --git a/hdl/modules/fofb_processing/cheby/dot_prod_wb.vhd b/hdl/modules/fofb_processing/cheby/dot_prod_wb.vhd
diff --git a/...s/fofb_processing/cheby/dot_prod_wb.cheby → ...ssing/cheby/wb_fofb_processing_regs.cheby b/...s/fofb_processing/cheby/dot_prod_wb.cheby → ...ssing/cheby/wb_fofb_processing_regs.cheby
@@ -1,6 +1,6 @@
 memory-map:
   bus: wb-32-be
-  name: dot_prod_wb
+  name: wb_fofb_processing_regs
   description: interface to memory
   children:
   - reg:
@@ -10,15 +10,15 @@ memory-map:
       access: rw
       x-wbgen:
         type: SLV
-        clock: dot_prod_clk_reg_i
+        clock: fofb_processing_clk_reg_i
   - reg:
       name: ram_coeff_addr
       address: 0x00000004
       width: 32
       access: rw
       x-wbgen:
         type: SLV
-        clock: dot_prod_clk_reg_i
+        clock: fofb_processing_clk_reg_i
   - reg:
       name: ram_write
       address: 0x00000008
@@ -32,4 +32,4 @@ memory-map:
             range: 0
             x-wbgen:
               type: MONOSTABLE
-              clock: dot_prod_clk_reg_i
+              clock: fofb_processing_clk_reg_i
diff --git a/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h b/hdl/modules/fofb_processing/cheby/wb_fofb_processing_regs.h
@@ -0,0 +1,26 @@
+#ifndef __CHEBY__WB_FOFB_PROCESSING_REGS__H__
+#define __CHEBY__WB_FOFB_PROCESSING_REGS__H__
+#define WB_FOFB_PROCESSING_REGS_SIZE 12 /* 0xc */
+
+/* None */
+#define WB_FOFB_PROCESSING_REGS_RAM_COEFF_DAT 0x0UL
+
+/* None */
+#define WB_FOFB_PROCESSING_REGS_RAM_COEFF_ADDR 0x4UL
+
+/* None */
+#define WB_FOFB_PROCESSING_REGS_RAM_WRITE 0x8UL
+#define WB_FOFB_PROCESSING_REGS_RAM_WRITE_ENABLE 0x1UL
+
+struct wb_fofb_processing_regs {
+  /* [0x0]: REG (rw) (no description) */
+  uint32_t ram_coeff_dat;
+
+  /* [0x4]: REG (rw) (no description) */
+  uint32_t ram_coeff_addr;
+
+  /* [0x8]: REG (rw) (no description) */
+  uint32_t ram_write;
+};
+
+#endif /* __CHEBY__WB_FOFB_PROCESSING_REGS__H__ */