Release 0.48

lightside-instruments · Feb 9, 2023 · d2a971d · d2a971d
1 parent 8b75bc2
commit d2a971d
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Showing 6 changed files with 40 additions and 15 deletions.
diff --git a/CHANGELOG b/CHANGELOG
@@ -1,3 +1,10 @@
+network-interconnect-tester-cores (0.48) stable; urgency=medium
+
+  * Dedicated pins added for the alternative frequencies ref_clk_10mhz_or_12mhz (D5) replaced with ref_clk_10mhz (D5.HDGC) and ref_clk_12mhz (D7.HDGC)
+  * Enable second CS (MIO40) for spi0 e.g. /dev/spidev0.1
+
+ -- Vladimir Vassilev <[email protected]>  Thu, 09 Feb 2023 11:54:43 +0100
+
 network-interconnect-tester-cores (0.47) stable; urgency=medium
 
   * Changed ref_jitter for the clk_rst_i_plle3_tx and clk_rst_i_plle3_rx pcs/pma clock instantiation from 0.010 to 0.060

diff --git a/lib/sw/lsi/configure.ac b/lib/sw/lsi/configure.ac
@@ -1,4 +1,4 @@
-AC_INIT([network-interconnect-tester-cores-sw], [0.47], [[email protected]])
+AC_INIT([network-interconnect-tester-cores-sw], [0.48], [[email protected]])
 
 AC_CANONICAL_SYSTEM
 AM_INIT_AUTOMAKE([foreign])

diff --git a/systems/spark/design.tcl b/systems/spark/design.tcl
@@ -550,7 +550,8 @@ create_bd_port -dir I ls_mezz_int1
 
 # ref clk (10 MHz) signal from GPS e.g. gpsclock4ultra96
 #create_bd_port -dir I -type clk -freq_hz 10000000 ref_clk_10mhz
-create_bd_port -dir I ref_clk_10mhz_or_12mhz
+create_bd_port -dir I ref_clk_10mhz
+create_bd_port -dir I ref_clk_12mhz
 
 # PHY RESET for ports 0,1 and 2
 ##create_bd_port -dir O reset_port_0_n
@@ -1101,7 +1102,7 @@ connect_bd_net [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins
 connect_bd_net [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins traffic_analyzer_gmii_0/resetn]
 connect_bd_net [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins rtclock_0/resetn]
 
-#Add 10->10 MHz primary or 12->10MHz secondary clock input management tile (CMT) using the mixed-mode clock manager (MMCM)
+#Add 12->10 MHz primary or 10->10MHz secondary clock input management tile (CMT) using the mixed-mode clock manager (MMCM)
 create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_1
 set_property -dict [list CONFIG.PRIM_IN_FREQ.VALUE_SRC USER CONFIG.SECONDARY_IN_FREQ.VALUE_SRC USER] [get_bd_cells clk_wiz_1]
 set_property -dict [list CONFIG.USE_DYN_RECONFIG {true} CONFIG.JITTER_SEL {Max_I_Jitter} CONFIG.USE_INCLK_SWITCHOVER {true} CONFIG.PRIM_SOURCE {No_buffer} CONFIG.PRIM_IN_FREQ {12.000} CONFIG.SECONDARY_SOURCE {No_buffer} CONFIG.JITTER_OPTIONS {PS} CONFIG.CLKIN1_UI_JITTER {11000.000} CONFIG.CLKIN2_UI_JITTER {11000.000} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {10.000} CONFIG.SECONDARY_IN_FREQ {10.000} CONFIG.CLKIN1_JITTER_PS {11000.000} CONFIG.CLKIN2_JITTER_PS {11000.000} CONFIG.MMCM_BANDWIDTH {LOW} CONFIG.MMCM_CLKFBOUT_MULT_F {85.625} CONFIG.MMCM_CLKIN1_PERIOD {83.333} CONFIG.MMCM_CLKIN2_PERIOD {100.000} CONFIG.MMCM_REF_JITTER1 {0.132} CONFIG.MMCM_REF_JITTER2 {0.110} CONFIG.MMCM_CLKOUT0_DIVIDE_F {102.750} CONFIG.CLKOUT1_JITTER {5240.097} CONFIG.CLKOUT1_PHASE_ERROR {741.940}] [get_bd_cells clk_wiz_1]
@@ -1118,8 +1119,8 @@ set_property -dict [list CONFIG.USE_INCLK_SWITCHOVER {true} CONFIG.SECONDARY_IN_
 
 #connect_bd_net [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins ref_clk_10mhz]
 
-connect_bd_net [get_bd_ports ref_clk_10mhz_or_12mhz] [get_bd_pins clk_wiz_1/clk_in1]
-connect_bd_net [get_bd_ports ref_clk_10mhz_or_12mhz] [get_bd_pins clk_wiz_1/clk_in2]
+connect_bd_net [get_bd_ports ref_clk_12mhz] [get_bd_pins clk_wiz_1/clk_in1]
+connect_bd_net [get_bd_ports ref_clk_10mhz] [get_bd_pins clk_wiz_1/clk_in2]
 
 connect_bd_net [get_bd_pins clk_wiz_0/clk_in2] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
 connect_bd_net [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins clk_wiz_2/clk_out1]
@@ -1213,6 +1214,8 @@ connect_bd_net [get_bd_ports ls_mezz_int0] [get_bd_pins rtclock_1/pps]
 connect_bd_net [get_bd_ports ls_mezz_int1] [get_bd_pins rtclock_1/pps2]
 connect_bd_net [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins rtclock_1/resetn]
 
+#Enable second CS (MIO40) for spi0 e.g. /dev/spidev0.1
+set_property -dict [list CONFIG.PSU__SPI0__GRP_SS1__ENABLE {1}] [get_bd_cells zynq_ultra_ps_e_0]
 
 # Restore current instance
 current_bd_instance $oldCurInst

diff --git a/systems/spark/petalinux/build-petalinux b/systems/spark/petalinux/build-petalinux
@@ -81,6 +81,13 @@ fi
     do
       cat $f >> ./project-spec/configs/config
     done
+
+    # Off-line build - start
+#    sed -i "s/CONFIG_PRE_MIRROR_URL=.*/CONFIG_PRE_MIRROR_URL=\"\"/g" ./project-spec/configs/config
+#    echo 'DL_DIR = "/petalinux/downloads"' >> ./project-spec/meta-user/conf/petalinuxbsp.conf
+#    echo 'SSTATE_DIR = "/petalinux/sstate-cache"'  >> ./project-spec/meta-user/conf/petalinuxbsp.conf
+    # Off-line build - end
+
     # Append mods to rootfs_config file
     rootfs_config_mod_list=(`find ./project-spec/configs/ -name "rootfs_config*.append"`)
     for f in ${rootfs_config_mod_list[*]}

diff --git a/...rk/petalinux/src/v2/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi b/...rk/petalinux/src/v2/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
@@ -37,13 +37,18 @@
 
 &spi0 {
         is-decoded-cs = <0>;
-        num-cs = <1>;
+        num-cs = <2>;
         status = "okay";
         spidev@0x00 {
                 compatible = "rohm,dh2228fv";
                 spi-max-frequency = <1000000>;
                 reg = <0>;
         };
+        spidev@0x01 {
+                compatible = "rohm,dh2228fv";
+                spi-max-frequency = <1000000>;
+                reg = <1>;
+        };
 };
 
 &spi1 {

diff --git a/systems/spark/spark.xdc b/systems/spark/spark.xdc
@@ -3,6 +3,8 @@
 #     [2] Linaro 96Boards-CE-Specification.pdf v1.0 p.16-20
 #     [3] Avnet ultra96-schematics.pdf
 #     [4] Lightside Instruments spark-v1-schematics.pdf
+#     [5] https://docs.xilinx.com/v/u/en-US/ug1075-zynq-ultrascale-pkg-pinout
+#     [6] https://www.xilinx.com/support/packagefiles/zuppackages/xqzu3egsfra484pkg.txt
 #
 #     IO standard for Bank 26 Vcco supply is fixed at 1.8V
 #     IO standard for Bank 65 Vcco supply is fixed at 1.2V
@@ -198,8 +200,8 @@ set_property INTERNAL_VREF 0.60 [get_iobanks 65]
 # ports and then change the port names in the below constraints and uncomment them.
 # ---------------------------------------------------------------------------- 
 # Bank 23 (1.8V)
-#set_property PACKAGE_PIN D7   [get_ports {HD_GPIO_0}];  # "D7.HDGC_GPIO_0" UART0_CTS, PIN 3
-#set_property IOSTANDARD LVCMOS18 [get_ports {HD_GPIO_0}];
+set_property PACKAGE_PIN D7   [get_ports {ref_clk_12mhz}];  # "D7.HDGC_GPIO_0 - L5P" UART0_CTS, PIN 3
+set_property IOSTANDARD LVCMOS18 [get_ports {ref_clk_12mhz}];
 set_property PACKAGE_PIN F8   [get_ports {ls_mezz_uart0_tx}];  # "F8.HD_GPIO_1" UART0_TXD, PIN 5
 set_property IOSTANDARD LVCMOS18 [get_ports {ls_mezz_uart0_tx}];
 set_property PACKAGE_PIN F7   [get_ports {ls_mezz_uart0_rx}];  # "F7.HD_GPIO_2" UART0_RXD, PIN 7
@@ -220,15 +222,15 @@ set_property IOSTANDARD LVCMOS18 [get_ports {ls_mezz_int0}];
 #set_property IOSTANDARD LVCMOS18 [get_ports {HD_GPIO_9}];
 #set_property PACKAGE_PIN E5   [get_ports {HD_GPIO_10}];  # "E5.HD_GPIO_10" PCM_CLK, PIN 18
 #set_property IOSTANDARD LVCMOS18 [get_ports {HD_GPIO_10}];
-#set_property PACKAGE_PIN D6   [get_ports {HD_GPIO_11}];  # "D6.HDGC_GPIO_11" PCM_DO, PIN 20
+#set_property PACKAGE_PIN D6   [get_ports {HD_GPIO_11}];  # "D6.HDGC_GPIO_11 - L5N" PCM_DO, PIN 20
 #set_property IOSTANDARD LVCMOS18 [get_ports {HD_GPIO_11}];
-set_property PACKAGE_PIN D5   [get_ports {ref_clk_10mhz_or_12mhz}];  # "D5.HDGC_GPIO_12" PCM_DI, PIN 22
-set_property IOSTANDARD LVCMOS18 [get_ports {ref_clk_10mhz_or_12mhz}];
-##set_property PACKAGE_PIN C7   [get_ports {reset_port_1_n}];  # "C7.HDGC_GPIO_13" GPIO-H, PIN 30
-##set_property IOSTANDARD LVCMOS18 [get_ports {reset_port_1_n}];
+set_property PACKAGE_PIN D5   [get_ports {ref_clk_10mhz}];  # "D5.HDGC_GPIO_12 - L7P" PCM_DI, PIN 22
+set_property IOSTANDARD LVCMOS18 [get_ports {ref_clk_10mhz}];
+#set_property PACKAGE_PIN C7   [get_ports {reset_port_1_n}];  # "C7.HDGC_GPIO_13 - L8N" GPIO-H, PIN 30
+#set_property IOSTANDARD LVCMOS18 [get_ports {reset_port_1_n}];
 ##set_property PACKAGE_PIN B6   [get_ports {reset_port_3_n}];  # "B6.HD_GPIO_14" GPIO-J, PIN 32
 ##set_property IOSTANDARD LVCMOS18 [get_ports {reset_port_3_n}];
-set_property PACKAGE_PIN C5   [get_ports {ls_mezz_int1}];  # "C5.HDGC_GPIO_15" GPIO-L, PIN 34
+set_property PACKAGE_PIN C5   [get_ports {ls_mezz_int1}];  # "C5.HDGC_GPIO_15 - L7N" GPIO-L, PIN 34
 set_property IOSTANDARD LVCMOS18 [get_ports {ls_mezz_int1}];
 
 #set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets *_i/eth_pcs_pma_3_rx/inst/clock_reset_i/iclkbuf/O]
@@ -263,7 +265,8 @@ set_property ODT RTT_48 [get_ports sfp_port_5_rx_rxn]
 #set_property ODT RTT_48 [get_ports ref_clk_625mhz_clk_p]
 #set_property ODT RTT_48 [get_ports ref_clk_625mhz_clk_n]
 
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ref_clk_10mhz_or_12mhz]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ref_clk_10mhz]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ref_clk_12mhz]
 
 # Bluetooth UART0 pins
 set_property IOSTANDARD LVCMOS18 [get_ports BT*]