A revision of the LSC that enables its usage in resource estimation for Clifford+T circuits as described in the Realistic Costs... paper. Some highlights include:
- The wave pipeline (-P wave), which detects circuit-level parallelism using a directed acyclic graph (DAG) and translates it into FT-encoded circuit parallelism while respecting layout-imposed restrictions on the routing space and the availability of magic states
- Optionally decomposes long-range CNOT gates into local pair-wise lattice surgery-based primitives (--local)
- Improved output format (--printlli sliced) that reflects both parallel LLI acting on patch IDs at particular time-slices and (optionally) their associated local primitive operations acting on layout tiles
- An improved, parametrized layout generator that enables the exploration of space-time trade-offs through changing data:ancilla qubit ratios (-L edpc --numlanes xx --condensed yy)
- More flexible magic state handling that enables post-hoc optimization of magic state distillation and storage resources. In particular, magic states can be made available to user-specified tiles at a user-specified rate such that compilation determines the exact magic state consumption profile without factories needing to be specified up front
- Several options for S gate compilation that may depend on the layout used
Beyond the revisions from the Realistic Costs... paper, we also now provide an option for edge-disjoint path compilation of parallel CNOT gates through the -P edpc option.