Add “Avoid 4-Wire Kelvin Test” rule.

JLCPCB/JLCPCB.kicad_dru

@@ -79,6 +79,13 @@
 	(constraint annular_width (min 0.25mm))
 )
 
+# An expensive 4-Wire Kelvin Test is automatically added for holes that are < 0.3mm with a diameter ≤ 0.4mm.
+(rule "Avoid 4-Wire Kelvin Test"
+	(condition "(A.Type == 'Via' && A.Hole < 0.3mm && A.Diameter <= 0.4mm) || (A.Type == 'Pad' && ((A.Hole_Size_X < 0.3mm && A.Size_X <= 0.4mm) || (A.Hole_Size_Y < 0.3mm && A.Size_Y <= 0.4mm)))")
+  # 4-6 Layers
+  (constraint annular_width (min 0.125mm))
+)
+
 
 # --- Minimum Clearance ---
 

JLCPCB/JLCPCB.kicad_pcb

@@ -242,6 +242,21 @@
       (net 1 "+5V") (tstamp 524c74fc-eb91-418e-af2d-ea0edda34bf3))
   )
 
+  (footprint "" (layer "F.Cu")
+    (tstamp 4faa5a5e-b0d9-4fa9-9132-87d32c1c48b6)
+    (at 143.95 126.63)
+    (fp_text reference "" (at 0 0) (layer "F.SilkS")
+        (effects (font (size 1.27 1.27) (thickness 0.15)))
+      (tstamp bcbcb399-af2f-4076-8cc4-6dc3de6dc938)
+    )
+    (fp_text value "" (at 0 0) (layer "F.SilkS")
+        (effects (font (size 1.27 1.27) (thickness 0.15)))
+      (tstamp a212801c-b169-456f-b293-c94fe0928ac8)
+    )
+    (pad "" thru_hole rect (at 0.05 -0.13) (size 0.45 0.45) (drill 0.2) (layers "*.Cu" "*.Mask")
+      (pinfunction "VCC") (pintype "passive") (tstamp e37f0f3a-fef6-44fa-a3ca-468c2ff9288c))
+  )
+
   (footprint "MountingHole:MountingHole_2.2mm_M2_DIN965_Pad_TopBottom" (layer "F.Cu")
     (tstamp 581fa8cc-3dc3-43fc-bda1-88c961d747d2)
     (at 128 119)
@@ -263,6 +278,21 @@
     (pad "1" thru_hole circle (at 0 0) (size 1 1) (drill 0.59) (property pad_prop_castellated) (layers "*.Cu" "*.Mask") (tstamp a9a2445f-cf30-4e10-8f11-6156f08505da))
   )
 
+  (footprint "" (layer "F.Cu")
+    (tstamp 58e211ac-fe95-40bc-90f6-59b6c476157c)
+    (at 143.01 126.63)
+    (fp_text reference "" (at 0 0) (layer "F.SilkS")
+        (effects (font (size 1.27 1.27) (thickness 0.15)))
+      (tstamp 93da58cd-40d4-4e48-92e1-8bf84c6e5506)
+    )
+    (fp_text value "" (at 0 0) (layer "F.SilkS")
+        (effects (font (size 1.27 1.27) (thickness 0.15)))
+      (tstamp 9029c7b2-b9e8-4033-83d4-7e166bb28457)
+    )
+    (pad "" thru_hole circle (at -0.01 -0.13) (size 0.45 0.45) (drill 0.2) (layers "*.Cu" "*.Mask")
+      (pinfunction "VCC") (pintype "passive") (tstamp e37f0f3a-fef6-44fa-a3ca-468c2ff9288c))
+  )
+
   (footprint "MountingHole:MountingHole_2.2mm_M2_DIN965_Pad_TopBottom" (layer "F.Cu")
     (tstamp 5d3d9993-0244-4392-a86d-fac4f7d62f30)
     (at 143 169.9)
@@ -623,6 +653,21 @@
     (pad "1" thru_hole circle (at 0 0) (size 1 1) (drill 0.86) (property pad_prop_castellated) (layers "*.Cu" "*.Mask") (tstamp e913ab81-6a2e-4c98-b2e5-1576e81399ff))
   )
 
+  (footprint "" (layer "F.Cu")
+    (tstamp d783a6c5-271f-4717-8b2a-cfd59bb81cff)
+    (at 119 126.5)
+    (fp_text reference "" (at 0 0) (layer "F.SilkS")
+        (effects (font (size 1.27 1.27) (thickness 0.15)))
+      (tstamp ad3c321b-42e0-44fe-a4a5-c1b707ac4884)
+    )
+    (fp_text value "" (at 0 0) (layer "F.SilkS")
+        (effects (font (size 1.27 1.27) (thickness 0.15)))
+      (tstamp dec7bcb0-3214-4e78-967a-3b5088e1e9bb)
+    )
+    (pad "" thru_hole circle (at 0 0) (size 0.4 0.4) (drill 0.2) (layers "*.Cu" "*.Mask")
+      (pinfunction "VCC") (pintype "passive") (tstamp e37f0f3a-fef6-44fa-a3ca-468c2ff9288c))
+  )
+
   (footprint "MountingHole:MountingHole_2.2mm_M2_DIN965_Pad_TopBottom" (layer "F.Cu")
     (tstamp e186c5a8-f110-45e9-856b-8fa5d9865fb1)
     (at 124 99)
@@ -751,6 +796,21 @@
     (pad "1" thru_hole circle (at 0 0) (size 1 1) (drill 0.85) (property pad_prop_castellated) (layers "*.Cu" "*.Mask") (tstamp fe783d36-0b0f-4e02-b47f-9c8b1cae8e73))
   )
 
+  (footprint "" (layer "F.Cu")
+    (tstamp fc7c976c-7fbb-43dd-b087-9976896c77c7)
+    (at 120 126.5)
+    (fp_text reference "" (at 0 0) (layer "F.SilkS")
+        (effects (font (size 1.27 1.27) (thickness 0.15)))
+      (tstamp 6df69156-1172-4b2c-85eb-2f41fece3195)
+    )
+    (fp_text value "" (at 0 0) (layer "F.SilkS")
+        (effects (font (size 1.27 1.27) (thickness 0.15)))
+      (tstamp 856c2066-aa47-44b1-bf01-5a418ead323a)
+    )
+    (pad "" thru_hole rect (at 0 0) (size 0.4 0.4) (drill 0.2) (layers "*.Cu" "*.Mask")
+      (pinfunction "VCC") (pintype "passive") (tstamp e37f0f3a-fef6-44fa-a3ca-468c2ff9288c))
+  )
+
   (footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P2.54mm_Vertical" (layer "F.Cu")
     (tstamp fec7a672-0c2b-48ff-926b-c9c0a38d9237)
     (at 129 17)
@@ -936,7 +996,9 @@
     (stroke (width 0.1) (type solid))  )
 
   (via (at 141 129) (size 0.5) (drill 0.35) (layers "F.Cu" "B.Cu") (free) (net 0) (tstamp 09be0d16-05ed-4ed9-88ad-5430988a59cd))
+  (via (at 118 126.5) (size 0.4) (drill 0.2) (layers "F.Cu" "B.Cu") (free) (net 0) (tstamp 95fdb70d-4619-4e3a-b09e-7fc14449017b))
   (via (at 121 129) (size 0.5) (drill 0.36) (layers "F.Cu" "B.Cu") (free) (net 0) (tstamp 9b9a1e43-ba8e-4f49-a6a4-0c75a75c17a1))
+  (via (at 142 126.5) (size 0.45) (drill 0.2) (layers "F.Cu" "B.Cu") (free) (net 0) (tstamp f3864973-a9cf-43cc-a3f0-a6b8fc63deee))
   (segment (start 135.29 35) (end 137 33.29) (width 0.2) (layer "F.Cu") (net 1) (tstamp 0b2714b6-7f56-48fb-a8e4-9869b7576904))
   (segment (start 131 35) (end 130.71 35) (width 0.2) (layer "F.Cu") (net 1) (tstamp 306442e7-e0c2-4d09-b1ee-71c16baeac5b))
   (segment (start 137 33.29) (end 141 33.29) (width 0.2) (layer "F.Cu") (net 1) (tstamp 59514570-f4f6-4597-ae99-bc023e8b7149))

JLCPCB/JLCPCB.kicad_pro

@@ -34,9 +34,9 @@
         "other_text_thickness": 0.15,
         "other_text_upright": false,
         "pads": {
-          "drill": 0.86,
-          "height": 1.0,
-          "width": 1.0
+          "drill": 0.2,
+          "height": 0.45,
+          "width": 0.45
         },
         "silk_line_width": 0.15,
         "silk_text_italic": false,