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kholoud0/README.md

๐Ÿ‘‹ Hi, i'm Kholoud


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๐Ÿง‘โ€๐Ÿ’ป About me

  • I am Kholoud Khaled, a fresh Electronics and Communication Engineering graduate from Ain Shams University. I specialize in Digital IC design and am passionate about contributing to innovative projects in this field. My experiences range from ASIC Design & Verification to implementation, and I am always eager to learn and grow in the ever-evolving world of electronics.

๐Ÿ› ๏ธ Technical Skills

  • Languages: Verilog, VHDL, SystemVerilog, TCL, Python, C, C++

  • Tools: Synopsys Design Compiler, DFT Compiler, IC Compiler II, PrimeTime, ModelSim, Vivado, MATLAB, Cadence Virtuoso, OpenLane

  • Key Concepts: ASIC Flow, RTL Coding, Static Timing Analysis (STA), Place and Route (PnR), DFT, Low Power Design, Formal Verification, UVM


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