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Bug: false errors on duplicate on component instantiation parameter
bug
#110
opened May 17, 2024 by
Kyrhe
Configuring VHDL Generator to use entity instantiation.
feature request
#70
opened Oct 11, 2022 by
andrewandrepowell
Navigating components is very slow with 100s of ports.
enhancement
#51
opened Feb 13, 2022 by
TonyReinberger
HW Component generate of VHDL does not use parameters for port signals.
#47
opened Feb 7, 2022 by
TonyReinberger
SystemVerilog expressions evaluator has strange signed results in bit vector fields (resets->value,mask)
bug
#35
opened Dec 31, 2019 by
mwsealey
Kactus doesn't correctly deal with XML namespaces
enhancement
feature request
#31
opened Aug 31, 2019 by
andreasWallner
ProTip!
Updated in the last three days: updated:>2024-11-22.