test

info.yaml

@@ -5,10 +5,9 @@ project:
 
 # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. 
 # Source files must be in ./src and you must list each source file separately
-#  source_files:        
-#    - counter.v
-#    - decoder.v
-#  top_module:  "tt_um_example"      # Put the name of your top module here, must start with "tt_um_". Make it unique by including your github username
+  source_files:        
+    - tt_um_nand.sv
+  top_module:  "tt_um_nand"      # Put the name of your top module here, must start with "tt_um_". Make it unique by including your github username
 
 # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"    # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2 or 8x2

src/Makefile

@@ -0,0 +1,41 @@
+# Makefile
+# See https://docs.cocotb.org/en/stable/quickstart.html for more info
+
+.PHONY: simulate convert all
+
+# defaults
+SIM ?= icarus
+TOPLEVEL_LANG ?= verilog
+
+# normal simulation
+ifneq ($(GATES),yes)
+
+# this is the only part you should need to modify:
+VERILOG_SOURCES += $(PWD)/tt_um_nand.sv
+
+else
+
+# gate level simulation requires some extra setup, you shouldn't need to touch this
+COMPILE_ARGS    += -DGL_TEST
+COMPILE_ARGS    += -DFUNCTIONAL
+COMPILE_ARGS    += -DUSE_POWER_PINS
+COMPILE_ARGS    += -DSIM
+COMPILE_ARGS    += -DUNIT_DELAY=\#1
+VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
+VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
+
+# this gets copied in by the GDS action workflow
+VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/gate_level_netlist.v
+endif
+
+# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
+TOPLEVEL = tb
+
+# MODULE is the basename of the Python test file
+MODULE = test
+
+# include cocotb's make rules to take care of the simulator setup
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+convert: $(FILE).sv
+	yosys "-p read_verilog -sv $(FILE).sv; write_verilog $(FILE).v"

src/tt_um_nand.sv

@@ -0,0 +1,29 @@
+//==============================================================================
+//
+// The code is generated by Intel Compiler for SystemC, version 1.5.15
+// see more information at https://github.com/intel/systemc-compiler
+//
+//==============================================================================
+
+//==============================================================================
+//
+// Module: nand_gate ()
+//
+module tt_um_nand // "tb.dut_inst"
+(
+    input logic A,
+    input logic B,
+    output logic Z
+);
+
+//------------------------------------------------------------------------------
+// Method process: do_nand (nand_gate.h:11:5) 
+
+always_comb 
+begin : do_nand     // nand_gate.h:11:5
+    Z = !(A && B);
+end
+
+endmodule
+
+