Reset tests to template

src/tb.v

@@ -1,39 +1,27 @@
 `default_nettype none
 `timescale 1ns/1ps
 
-/*
-this testbench just instantiates the module and makes some convenient wires
-that can be driven / tested by the cocotb test.py
-*/
+module tb (
+    );
 
-// testbench is controlled by test.py
-module tb ();
-
-    // this part dumps the trace to a vcd file that can be viewed with GTKWave
     initial begin
         $dumpfile ("tb.vcd");
         $dumpvars (0, tb);
         #1;
     end
 
-    // wire up the inputs and outputs
+    // wire up inputs and outputs. Use reg for inputs that will be driven by the testbench.
     reg  clk;
     reg  rst_n;
     reg  ena;
     reg  [7:0] ui_in;
     reg  [7:0] uio_in;
 
-    wire [6:0] segments = uo_out[6:0];
     wire [7:0] uo_out;
     wire [7:0] uio_out;
     wire [7:0] uio_oe;
 
-    tt_um_seven_segment_seconds tt_um_seven_segment_seconds (
-    // include power ports for the Gate Level test
-    `ifdef GL_TEST
-        .VPWR( 1'b1),
-        .VGND( 1'b0),
-    `endif
+    toplevel_module toplevel_module (
         .ui_in      (ui_in),    // Dedicated inputs
         .uo_out     (uo_out),   // Dedicated outputs
         .uio_in     (uio_in),   // IOs: Input path
@@ -43,5 +31,6 @@ module tb ();
         .clk        (clk),      // clock
         .rst_n      (rst_n)     // not reset
         );
+    );
 
 endmodule

src/test.py

@@ -3,46 +3,6 @@
 from cocotb.triggers import RisingEdge, FallingEdge, Timer, ClockCycles
 
 
-segments = [ 63, 6, 91, 79, 102, 109, 124, 7, 127, 103 ]
-
 @cocotb.test()
 async def test_7seg(dut):
-    dut._log.info("start")
-    clock = Clock(dut.clk, 10, units="us")
-    cocotb.start_soon(clock.start())
-
-    # reset
-    dut._log.info("reset")
-    dut.rst_n.value = 0
-    # set the compare value
-    dut.ui_in.value = 1
-    await ClockCycles(dut.clk, 10)
-    dut.rst_n.value = 1
-
-    # the compare value is shifted 10 bits inside the design to allow slower counting
-    max_count = dut.ui_in.value << 10
-    dut._log.info(f"check all segments with MAX_COUNT set to {max_count}")
-    # check all segments and roll over
-    for i in range(15):
-        dut._log.info("check segment {}".format(i))
-        await ClockCycles(dut.clk, max_count)
-        assert int(dut.segments.value) == segments[i % 10]
-
-        # all bidirectionals are set to output
-        assert dut.uio_oe == 0xFF
-
-    # reset
-    dut.rst_n.value = 0
-    # set a different compare value
-    dut.ui_in.value = 3
-    await ClockCycles(dut.clk, 10)
-    dut.rst_n.value = 1
-
-    max_count = dut.ui_in.value << 10
-    dut._log.info(f"check all segments with MAX_COUNT set to {max_count}")
-    # check all segments and roll over
-    for i in range(15):
-        dut._log.info("check segment {}".format(i))
-        await ClockCycles(dut.clk, max_count)
-        assert int(dut.segments.value) == segments[i % 10]
-
+    dut._log.info("start")