Update chisel3.5

.travis.yml

@@ -1,25 +1,16 @@
 name: Scratchip Binary CI
 language: generic
 env:
-  - VER=3.3.2 MILL_VERSION=0.7.3
+  - MILL_VERSION=0.10.0
 before_deploy:
   - curl --fail -L -o mill https://github.com/lihaoyi/mill/releases/download/$MILL_VERSION/$MILL_VERSION-assembly
   - chmod +x mill
-  - wget https://github.com/freechipsproject/chisel3/archive/v$VER.zip
-  - unzip v$VER.zip
-  - cd chisel3-$VER
-  - ../mill chisel3[2.12.11].assembly
-  - mv out/chisel3/2.12.11/assembly/dest/out-tmp.jar chisel3-$VER.jar
-  - cd ..
-  - mkdir -p lib
-  - cp chisel3-$VER/chisel3-$VER.jar lib
   - make verilog
   - tar czvf cache.tar.gz .cache
 deploy:
   provider: releases
   api_key: $GITHUB_TOKEN
   file:
-    - lib/chisel3-$VER.jar
     - cache.tar.gz
     - mill
   skip_cleanup: true

build.sc

@@ -1,20 +1,32 @@
 import mill._, scalalib._
-import ammonite.ops._
 import java.nio.file.Paths
 
 object chisel extends ScalaModule {
-  def scalaVersion = "2.12.6"
+  def scalaVersion = "2.13.8"
   def scalacOptions = Seq(
-    "-Xsource:2.11",
+    "-language:reflectiveCalls",
+    "-deprecation",
+    "-feature",
+    "-Xcheckinit",
+    "-P:chiselplugin:genBundleElements"
+  )
+
+  def millSourcePath = super.millSourcePath / os.up
+
+  override def ivyDeps = Agg(
+    ivy"edu.berkeley.cs::chisel3:3.5.1",
+  )
+
+  override def scalacPluginIvyDeps = Agg(
+    ivy"edu.berkeley.cs:::chisel3-plugin:3.5.1",
   )
-  def millSourcePath = super.millSourcePath / ammonite.ops.up
 
   def unmanagedClasspath = T {
     val lib_path = T.ctx.env.get("MILL_LIB") match {
-      case Some(lib) => Path(Paths.get(lib).toAbsolutePath)
+      case Some(lib) => os.Path(Paths.get(lib).toAbsolutePath)
       case None      => millSourcePath / "lib"
     }
-    if (!ammonite.ops.exists(lib_path)) Agg()
-    else Agg.from(ammonite.ops.ls(lib_path).map(PathRef(_)))
+    if (!os.exists(lib_path)) Agg()
+    else Agg.from(os.list(lib_path).map(PathRef(_)))
   }
-}
+}

src/Top.scala

@@ -16,5 +16,6 @@ class Top extends Module {
 }
 
 object Main extends App {
-  Driver.execute(args, () => new Top)
+  (new chisel3.stage.ChiselStage)
+    .emitVerilog(new Top, args)
 }