ECE 5745 Tutorial 6: Automated ASIC Flow

This repository contains the code and documentation for ECE 5745 Tutorial 6 on the automated ASIC flow. Tutorial 5 introduced students to the key tools used for synthesis, place-and-route, simulation, and power analysis, but this previous tutorial required students to enter commands manually for each tool. This is obviously very tedious and error prone. An agile hardware design flow demands automation to simplify rapidly exploring the area, energy, timing design space of one or more designs. Luckily, Synopsys and Cadence tools can be easily scripted using TCL, and even better, the ECE 5745 staff have created steps for automating the entire flow using mflowgen.

You can find the actual tutorial document in the repo here:

• docs/index.md

Or online here:

• https://cornell-ece5745.github.io/ece5745-tut6-asic-flow