A 5-stage pipelined mips32 processor
·Finished as a final project for the course "Computer Architecture" in Beihang University.
·FGPA configuration
Family: Spartan6
Device: XC6SLX100
Package: FGG676
Speed: -2
·Instructions supported:
LB、LBU、LH、LHU、LW、SB、SH、SW、ADD、ADDU、SUB、SUBU、SLL、SRL、SRA、SLLV、SRLV、SRAV、 AND、OR、XOR、NOR、ADDI、ADDIU、ANDI、ORI、XORI、LUI、SLT、SLTI、 SLTIU、SLTU、BEQ、BNE、BLEZ、BGTZ、BLTZ、BGEZ、J、JAL、JALR、JR、ERET、MFC0、MTC0
·Interruption supported (Timer and MiniUART can send interruption requests)
·Serial Communication through MiniUART module (RS-232 prototype)
·Forwarding as long as it's possible. Stalling when needed.
