Integer

CONTRIBUTING.md

@@ -48,7 +48,7 @@ You must have [Dart](https://dart.dev/) installed on your system to use ROHD and
 
 #### On your own system
 
-[Visual Studio Code (VSCode)](https://code.visualstudio.com/) is a great IDE for development. You can find installation instructions for VSCode here: <https://code.visualstudio.com/Download>
+[Visual Studio Code (VSCode)](https://code.visualstudio.com/) is a great IDE for development. You can find installation instructions for VSCode here: <https://visualstudio.microsoft.com/#vscode-section>
 
 The Dart extension extends VSCode with support for the Dart programming language and provides tools for effectively editing, refactoring and running. Check out the detailed information: <https://dartcode.org/>
 
@@ -131,7 +131,7 @@ Please include the SPDX tag near the top of any new files you create:
 Here is an example of a recommended file header template:
 
 ```dart
-// Copyright (C) 2021-2023 Intel Corporation
+// Copyright (C) 2021-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // example.dart

README.md

@@ -52,5 +52,5 @@ Some examples of component categories include:
 
 ----------------
 
-Copyright (C) 2023 Intel Corporation  
+Copyright (C) 2023-2024 Intel Corporation
 SPDX-License-Identifier: BSD-3-Clause

confapp/README.md

@@ -11,5 +11,5 @@ flowchart TD;
 
 ----------------
 
-Copyright (C) 2023 Intel Corporation  
+Copyright (C) 2023-2024 Intel Corporation
 SPDX-License-Identifier: BSD-3-Clause

confapp/lib/app.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // app.dart

confapp/lib/hcl/cubit/component_cubit.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // component_cubit.dart

confapp/lib/hcl/cubit/system_verilog_cubit.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // system_verilog_cubit.dart

confapp/lib/hcl/hcl.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 
 export 'view/hcl_page.dart';

confapp/lib/hcl/view/hcl_page.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // hcl_page.dart

confapp/lib/hcl/view/hcl_view.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // hcl_view.dart

confapp/lib/hcl/view/screen/content_widget.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // content_widget.dart

confapp/lib/hcl/view/screen/sidebar_widget.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // sidebar_widget.dart

confapp/lib/hcl_bloc_observer.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // hcl_bloc_observer.dart

confapp/lib/main.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // main.dart

confapp/test/example_component.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // example_component.dart

confapp/test/hcl/view/hcl_page_test.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // hcl_page_test.dart

doc/README.md

@@ -3,7 +3,7 @@
 
 Below is a list of components grouped by category. Ones with links are documented and completed, while others are still in planning or development stages.
 
-Some in-development items will have opened issues, as well. Feel free to create a pull request or file issues to add more ideas to this list. If you plan to develop and contribute a component, please be sure to open an issue so that there's not multiple people working on the same thing. Make sure to check if someone else has an open issue for a certain component before starting.
+Some in-development items will have opened issues, as well. Feel free to create a pull request or file issues to add more ideas to this list. If you plan to develop and contribute a component, please be sure to open an issue so that there are not multiple people working on the same thing. Make sure to check if someone else has an open issue for a certain component before starting.
 
 - Encoders & Decoders
   - [1-hot to Binary](./components/onehot.md)
@@ -25,18 +25,23 @@ Some in-development items will have opened issues, as well. Feel free to create
   - Find maximum
   - Find N'th pattern from the start/end
 - Count
-  - [Count bit occurence](./components/count.md)
-  - Count pattern occurence
+  - [Count bit occurrence](./components/count.md)
+  - Count pattern occurrence
 - Detection
   - [Edge detection](./components/edge_detector.md)
 - Sort
   - [Bitonic sort](./components/sort.md#bitonic-sort)
 - Arithmetic
   - [Prefix Trees](./components/parallel_prefix_operations.md)
   - [Adders](./components/adder.md)
+    - [Sign Magnitude Adder](./components/adder.md#ripple-carry-adder)
   - Subtractors
+    - [One's Complement Adder Subtractor](./components/adder.md#ones-complement-adder-subtractor)
   - Multipliers
     - [Pipelined Integer Multiplier](./components/multiplier.md#carry-save-multiplier)
+    - [Compression Tree Multiplier](./components/multiplier.md#compression-tree-multiplier)
+    - [Compression Tree Multiply-Accumulate](./components/multiplier.md#compression-tree-multiply-accumulate)
+    - [Booth Encoding and Compression Components](./components/multiplier_components.md)
   - Dividers
   - Log
   - Square root

doc/components/adder.md

@@ -1,14 +1,17 @@
 # Adder
 
-ROHD HCL provides an adder module to get the sum from a list of logic. As of now, we have
+ROHD-HCL provides a set of adder modules to get the sum from a pair of Logic. As of now, we have
 
 - [Ripple Carry Adder](#ripple-carry-adder)
+- [Parallel Prefix Adder](#parallel-prefix-adder)
+- [One's Complement Adder Subtractor](#ones-complement-adder-subtractor)
+- [Sign Magnitude Adder](#sign-magnitude-adder)
 
 ## Ripple Carry Adder
 
 A ripple carry adder is a digital circuit used for binary addition. It consists of a series of full adders connected in a chain, with the carry output of each adder linked to the carry input of the next one. Starting from the least significant bit (LSB) to most significant bit (MSB), the adder sequentially adds corresponding bits of two binary numbers.
 
-The [`RippleCarryAdder`](https://intel.github.io/rohd-hcl/rohd_hcl/RippleCarryAdder-class.html) module in ROHD-HCL accept input  `Logic`s a and b as the input pin and the name of the module `name`. Note that the width of the inputs must be the same or a `RohdHclException` will be thrown.
+The [`RippleCarryAdder`](https://intel.github.io/rohd-hcl/rohd_hcl/RippleCarryAdder-class.html) module in ROHD-HCL accept input `Logic`s a and b as the input pin and the name of the module `name`. Note that the width of the inputs must be the same or a `RohdHclException` will be thrown.
 
 An example is shown below to add two inputs of signals that have 8-bits of width.
 
@@ -22,3 +25,80 @@ b.put(5);
 final rippleCarryAdder = RippleCarryAdder(a, b);
 final sum = rippleCarryAdder.sum;
 ```
+
+## Parallel Prefix Adder
+
+A parallel prefix adder is an adder that uses different varieties of a parallel prefix tree (see `Parallel Prefix Operations`) to efficiently connect a set of `Full Adder` circuits to form a complete adder.
+
+Here is an example of instantiating a `ParallelPrefixAdder`:
+
+```dart
+    const width = 6;
+    final a = Logic(name: 'a', width: width);
+    final b = Logic(name: 'b', width: width);
+
+    a.put(18);
+    b.put(24);
+
+    final adder = ParallelPrefixAdder(a, b, ppGen: BrentKung.new);
+
+    final sum = adder.sum;
+
+    print('${sum.value.toBigInt()}');
+```
+
+## One's Complement Adder Subtractor
+
+A ones-complement adder (and subtractor) is useful in efficient arithmetic operations as the
+end-around carry can be bypassed and used later.
+
+The `OnesComplementAdder` can take a subtraction command as either a Logic `subtractIn` or a boolean `subtract` (the Logic overrides the boolean).  If Logic `carry` is provided, the end-around carry is output on `carry` and the value will be one less than expected when `carry` is high.  An `adderGen` adder function can be provided that generates your favorite internal adder (such as a parallel prefix adder).
+
+The output of `OnesComplementAdder` is a `sum` which is the magnitude and a `sign`.
+
+Here is an example of instantiating a `OnesComplementAdder` as a subtractor, but saving the `carry`:
+
+```dart
+    const width = 4;
+    final a = Logic(width: width);
+    final b = Logic(width: width);
+
+    a.put(av);
+    b.put(bv);
+    final carry = Logic();
+    final adder = OnesComplementAdder(
+        a, b, carryOut: carry, adderGen: RippleCarryAdder.new,
+        subtract: true);
+    final mag = adder.sum.value.toInt() + (carry.value.isZero ? 0 : 1));
+    final out = (adder.sign.value.toInt() == 1 ? -mag : mag);
+```
+
+## Sign Magnitude Adder
+
+A sign magnitude adder is useful in situations where the sign of the addends is separated from their magnitude (e.g., not 2s complement), such as in floating point multipliers.  The `SignMagnitudeAdder` inherits from `Adder` but adds the `Logic` inputs for the two operands.
+
+If you can supply the largest magnitude number first, then you can disable a comparator generation inside by declaring the `largestMagnitudeFirst` option as true.
+
+The `SignMagnitudeAdder` uses a `OnesComplementAdder` internally.
+
+Here is an example of instantiating a `SignMagnitudeAdder`:
+
+```dart
+    const width = 6;
+    final aSign = Logic(name: 'aSign');
+    final a = Logic(name: 'a', width: width);
+    final bSign = Logic(name: 'bSign');
+    final b = Logic(name: 'b', width: width);
+
+    aSign.put(1);
+    a.put(24);
+    b.put(18);
+    bSign.put(0);
+
+    final adder = SignMagnitudeAdder(aSign, a, bSign, b, adderGen: RippleCarryAdder.new,
+        largestMagnitudeFirst: true);
+
+    final sum = adder.sum;
+
+    print('${sum.value.toBigInt()}');
+```

doc/components/arbiter.md

@@ -1,6 +1,6 @@
 # Arbiters
 
-ROHD HCL implements a generic `abstract` [`Arbiter`](https://intel.github.io/rohd-hcl/rohd_hcl/Arbiter-class.html) class that other arbiters can extend.  It accepts a `List` of `requests`, where each request is a `1-bit` signal indicating that there is a request for a resource.  The output `grants` is a `List` where each element corresponds to the request with the same index.  The arbiter implementation decides how to select which request receives a grant.
+ROHD-HCL implements a generic `abstract` [`Arbiter`](https://intel.github.io/rohd-hcl/rohd_hcl/Arbiter-class.html) class that other arbiters can extend.  It accepts a `List` of `requests`, where each request is a `1-bit` signal indicating that there is a request for a resource.  The output `grants` is a `List` where each element corresponds to the request with the same index.  The arbiter implementation decides how to select which request receives a grant.
 
 ## Stateful Arbiter
 

doc/components/binary_gray.md

@@ -1,6 +1,6 @@
 # Binary Gray
 
-ROHD HCL provides a module to perform conversion on binary to gray and gray to binary.
+ROHD-HCL provides a module to perform conversion on binary to gray and gray to binary.
 
 ## Binary-to-Gray
 

doc/components/count.md

@@ -1,6 +1,6 @@
 # Count
 
-ROHD HCL comes with a `Count` component.  The detailed API docs are available [here](https://intel.github.io/rohd-hcl/rohd_hcl/rohd_hcl-library.html).
+ROHD-HCL comes with a `Count` component.  The detailed API docs are available [here](https://intel.github.io/rohd-hcl/rohd_hcl/rohd_hcl-library.html).
 
 A `Count` will count all one(`1`)/zero(`0`) within a given Logic `bus`.
 
@@ -12,7 +12,7 @@ This will return a Logic value labeled as `countOne` for `1` and `countZero` for
 
 ## Count One
 
-To count all ones just pass in the `bus` with `countOne` as `true`. By default countOne is `true`.
+To count all ones just pass in the `bus` with `countOne` as `true`. By default, `countOne` is `true`.
 
 ## Count Zero
 

doc/components/edge_detector.md

@@ -1,3 +1,3 @@
 # Edge Detection
 
-The `EdgeDetector` is a simple utility to determine whether the current value of a 1-bit signal is different from the value in the previous cycle.  It is a fully synchronous design, so it does not asynchronously detect edges.  It optionally supports a reset, with an optional reset value.  It can be configured to detect positive, negative, or "any" edges.
+The `EdgeDetector` is a simple utility to determine whether the current value of a 1-bit signal is different from the value in the previous cycle.  It is a fully synchronous design, so it does not asynchronously detect edges.  It optionally supports a reset, with an optional reset value.  Furthermore, it can be configured to detect positive, negative, or "any" edges.

doc/components/fifo.md

@@ -1,6 +1,6 @@
 # FIFO
 
-ROHD HCL comes with a simple FIFO (First In, First Out).  The detailed API docs are available [here](https://intel.github.io/rohd-hcl/rohd_hcl/Fifo-class.html).
+ROHD-HCL comes with a simple FIFO (First In, First Out).  The detailed API docs are available [here](https://intel.github.io/rohd-hcl/rohd_hcl/Fifo-class.html).
 
 The underlying implementation uses a flop-based memory (see [`RegisterFile`](https://intel.github.io/rohd-hcl/rohd_hcl/RegisterFile-class.html)) to store data until it is ready to be popped, with independent read and write pointers.
 
@@ -40,7 +40,7 @@ The FIFO comes with both a checker and a tracker that you can leverage in your t
 
 ### Checker
 
-The `FifoChecker` is a ROHD-VF component which will watch for proper usge of a FIFO in your simulation. It is intended to check usage, not  the internal workings of the FIFO, which are already pre-validated in the unit tests.  This means it covers things like underflow, overflow, and that the FIFO is empty at the end of the test.
+The `FifoChecker` is a ROHD-VF component which will watch for proper usage of a FIFO in your simulation. It is intended to check usage, not the internal workings of the FIFO, which are already pre-validated in the unit tests.  This means it covers things like underflow, overflow, and that the FIFO is empty at the end of the test.
 
 ### Tracker
 

doc/components/find.md

@@ -1,6 +1,6 @@
 # Find
 
-ROHD HCL comes with a Find.  The detailed API docs are available [here](https://intel.github.io/rohd-hcl/rohd_hcl/rohd_hcl-library.html).
+ROHD-HCL comes with a Find.  The detailed API docs are available [here](https://intel.github.io/rohd-hcl/rohd_hcl/rohd_hcl-library.html).
 
 A Find will search for first/nth occurrence of one(`1`)/zero(`0`) within a given Logic `bus`.
 The underlying implementation uses a `Count` to count 1's or 0's whenever a Logic `n` value
@@ -10,7 +10,7 @@ It takes a Binary Logic `bus` and finds the position of any one or zero within t
 That is to say, By default a Find will go for finding the first occurrence when no `n` is passed. In addition, with `countOne` which is set as `true` by default to
 search only one (`1`). Both boolean `countOne` and Logic `n` are optional. Only Logic `bus` is mandatory argument.
 
-This has an output pin named as `find`, for the index position on the occurrence searched (`1`s or `0`s) taken from the LSB (Least significant bit).
+This has an output pin named as `find`, for the index position on the occurrence searched (`1`s or `0`s) taken from the LSB (Least Significant Bit).
 
 ## Find First
 

doc/components/memory.md

@@ -1,6 +1,6 @@
 # Memory
 
-ROHD HCL provides a generic `abstract` [`Memory`](https://intel.github.io/rohd-hcl/rohd_hcl/Memory-class.html) class which accepts a dynamic number of `writePorts` and `readPorts`, where each port is of type [`DataPortInterface`](https://intel.github.io/rohd-hcl/rohd_hcl/DataPortInterface-class.html).  A `DataPortInterface` is a simple interface with `en` and `addr` as `control` signals and `data` signal(s).  In a write interface, all signals are in the same direction.  In a read interface, the `control` signals are in the opposite direction of the `data` signal(s).
+ROHD-HCL provides a generic `abstract` [`Memory`](https://intel.github.io/rohd-hcl/rohd_hcl/Memory-class.html) class which accepts a dynamic number of `writePorts` and `readPorts`, where each port is of type [`DataPortInterface`](https://intel.github.io/rohd-hcl/rohd_hcl/DataPortInterface-class.html).  A `DataPortInterface` is a simple interface with `en` and `addr` as `control` signals and `data` signal(s).  In a write interface, all signals are in the same direction.  In a read interface, the `control` signals are in the opposite direction of the `data` signal(s).
 
 ## Masks