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Fix memory model handling of different edge and latency situations #71

Merged
merged 2 commits into from
Jan 16, 2024
Merged

Fix memory model handling of different edge and latency situations #71

merged 2 commits into from
Jan 16, 2024

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mkorbel1
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Description & Motivation

This PR:

  • Fix bugs related to memory model sampling on negative edges and improper handling of zero-latency accesses.
  • Fix error handling and assertions in constructing Memory (e.g. bug where assertion fired incorrectly)
  • Updates doc/README with more components
  • Update APB tracker to have configurable widths for addr and data

Related Issue(s)

N/A

Testing

Added new tests

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

No

@mkorbel1 mkorbel1 merged commit 77b1c9d into intel:main Jan 16, 2024
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@mkorbel1 mkorbel1 deleted the memmodfix branch January 16, 2024 19:26
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@mkorbel1