Fix links for schematics

.github/workflows/general.yml

@@ -81,7 +81,7 @@ jobs:
         uses: flutter-actions/setup-flutter@v2
         with:
           channel: stable
-          version: 3.10.6
+          version: 3.16.3
 
       - name: Analyze flutter source
         run: tool/gh_actions/analyze_flutter_source.sh
@@ -148,7 +148,7 @@ jobs:
         uses: flutter-actions/setup-flutter@v2
         with:
           channel: stable
-          version: 3.10.6
+          version: 3.16.3
 
       - name: Build static site
         run: tool/gh_actions/hcl_site_generation_build.sh

doc/components/arbiter.md

@@ -6,7 +6,7 @@ ROHD HCL implements a generic `abstract` [`Arbiter`](https://intel.github.io/roh
 
 The [`PriorityArbiter`](https://intel.github.io/rohd-hcl/rohd_hcl/PriorityArbiter-class.html) is a combinational (stateless) arbiter that always grants to the lowest-indexed request.
 
-[PriorityArbiter Schematic](https://intel.github.io/rohd-hcl/PriorityArbiter.html)
+[PriorityArbiter Schematic](https://intel.github.io/rohd-hcl/Priority_Arbiter.html)
 
 ## Round Robin Arbiter
 

doc/components/fifo.md

@@ -32,7 +32,7 @@ Occupancy information can optionally be generated and provided if `generateOccup
 
 ## Example Schematic
 
-An example schematic for one configuration is viewable here: [FIFO Schematic](https://intel.github.io/rohd-hcl/Fifo.html)
+An example schematic for one configuration is viewable here: [FIFO Schematic](https://intel.github.io/rohd-hcl/FIFO.html)
 
 ## Testbench Utilities
 

doc/components/memory.md

@@ -16,7 +16,7 @@ Currently, `RegisterFile` only generates flop-based memory (no latches).
 
 The read path is combinational, so data is provided immediately according to the control signals.
 
-[RegisterFile Schematic](https://intel.github.io/rohd-hcl/RegisterFile.html)
+[RegisterFile Schematic](https://intel.github.io/rohd-hcl/Register_File.html)
 
 ## Memory Models
 

doc/components/onehot.md

@@ -8,8 +8,4 @@ The encoders take a Logic bitvector, with the constraint that only a single bit
 
 The decoders take a Logic input representing the bit position to be set to '1', and returns a Logic bitvector with that bit position set to '1', and all others set to '0'
 
-[BinaryToOneHot Schematic](https://intel.github.io/rohd-hcl/BinaryToOneHot.html)
-
-[OneHotToBinary Schematic](https://intel.github.io/rohd-hcl/OneHotToBinary.html)
-
-[TreeOneHotToBinary Schematic](https://intel.github.io/rohd-hcl/TreeOneHotToBinary.html)
+[OneHotToBinary Schematic](https://intel.github.io/rohd-hcl/One_hot_Converter.html)

doc/components/rotate.md

@@ -61,4 +61,4 @@ Also included are `extension`s for `LogicValue` with a similar rotation API for
 LogicValue.ofInt(0xf000, 16).rotateLeft(8); // results in 0x00f0
 ```
 
-[Rotateleft Schematic](https://intel.github.io/rohd-hcl/RotateLeft.html)
+[Rotate Right Schematic](https://intel.github.io/rohd-hcl/Rotate.html)