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Add some fixes for v1.5 #193

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Feb 29, 2024
Merged

Add some fixes for v1.5 #193

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4 changes: 3 additions & 1 deletion tdx-compliance/tdx-compliance-cpuid.h
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Original file line number Diff line number Diff line change
Expand Up @@ -304,7 +304,9 @@ void initial_cpuid(void)
EXP_CPUID_RES_BITS(0x7, 0x1, ecx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved

/* CPUID(0x7, 0x1).EDX */
EXP_CPUID_RES_BITS(0x7, 0x1, edx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved
EXP_CPUID_RES_BITS(0x7, 0x1, edx, 0, 31, VER2_0); //Reserved
EXP_CPUID_BIT(0x7, 0x1, edx, 4, 1, VER1_5);
EXP_CPUID_BIT(0x7, 0x1, edx, 5, 1, VER1_5);

/* CPUID(0x7, 0x2).EAX */
EXP_CPUID_RES_BITS(0x7, 0x2, eax, 0, 31, VER1_5); //Reserved
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12 changes: 8 additions & 4 deletions tdx-compliance/tdx-compliance-msr.h
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Expand Up @@ -322,8 +322,9 @@ struct test_msr msr_cases[] = {
DEF_WRITE_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x1, VER1_0 | VER1_5),
DEF_READ_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x1, VER2_0),
DEF_WRITE_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x1, VER2_0),
DEF_READ_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
DEF_WRITE_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
//TBD for v1.5: Not in SDM 2019_10 Arch. MSRs list.
DEF_READ_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon, VER2_0),
DEF_WRITE_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon, VER2_0),

DEF_WRITE_MSR(MSR_IA32_PERF_CAPABILITIES, X86_TRAP_GP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
DEF_READ_MSR(MSR_CORE_PERF_FIXED_CTR_CTRL, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
Expand All @@ -344,8 +345,11 @@ struct test_msr msr_cases[] = {
DEF_WRITE_MSR(MSR_PEBS_DATA_CFG, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
DEF_READ_MSR(MSR_PEBS_LD_LAT_THRESHOLD, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
DEF_WRITE_MSR(MSR_PEBS_LD_LAT_THRESHOLD, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
DEF_READ_MSR(MSR_PEBS_FRONTEND, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
DEF_WRITE_MSR(MSR_PEBS_FRONTEND, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),

//TBD for v1.5: Not in SDM 2019_10 Arch. MSRs list.
DEF_READ_MSR(MSR_PEBS_FRONTEND, NO_EXCP, pre_perfmon, VER2_0),
DEF_WRITE_MSR(MSR_PEBS_FRONTEND, NO_EXCP, pre_perfmon, VER2_0),

DEF_READ_MSR(MSR_IA32_VMX_BASIC, X86_TRAP_GP, NO_PRE_COND, VER1_0),
DEF_READ_MSR(MSR_IA32_VMX_BASIC, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0),
DEF_WRITE_MSR(MSR_IA32_VMX_BASIC, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0),
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