Fixed some cases version error.

Signed-off-by: DCyan_Elite <[email protected]>
intel · Nov 22, 2023 · 189f232 · 189f232
1 parent 941b09c
commit 189f232
Showing 1 changed file with 10 additions and 10 deletions.
diff --git a/tdx-compliance/tdx-compliance-msr.h b/tdx-compliance/tdx-compliance-msr.h
@@ -237,15 +237,15 @@ static void pre_fixedctr(struct test_msr *c)
 }
 
 struct test_msr msr_cases[] = {
-	DEF_READ_MSR(MSR_IA32_PLATFORM_ID, X86_TRAP_VE, NO_PRE_COND, VER1_5),
-	DEF_WRITE_MSR(MSR_IA32_PLATFORM_ID, X86_TRAP_VE, NO_PRE_COND, VER1_5),
+	DEF_READ_MSR(MSR_IA32_PLATFORM_ID, X86_TRAP_VE, NO_PRE_COND, VER1_5| VER2_0),
+	DEF_WRITE_MSR(MSR_IA32_PLATFORM_ID, X86_TRAP_VE, NO_PRE_COND, VER1_5| VER2_0),
 	/* according to MSR Index & Name, Ihis is a Guest behavior. */
-	DEF_READ_MSR(MSR_IA32_APICBASE, NO_EXCP, NO_PRE_COND, VER1_5),
-	DEF_WRITE_MSR(MSR_IA32_APICBASE, X86_TRAP_VE, NO_PRE_COND, VER1_5),
-	DEF_READ_MSR(MSR_TEST_CTRL, X86_TRAP_VE, NO_PRE_COND, VER1_5),
-	DEF_WRITE_MSR(MSR_TEST_CTRL, X86_TRAP_VE, NO_PRE_COND, VER1_5),
-	DEF_READ_MSR(MSR_IA32_TSC_ADJUST, X86_TRAP_VE, NO_PRE_COND, VER1_5),
-	DEF_WRITE_MSR(MSR_IA32_TSC_ADJUST, X86_TRAP_VE, NO_PRE_COND, VER1_5),
+	DEF_READ_MSR(MSR_IA32_APICBASE, NO_EXCP, NO_PRE_COND, VER1_5| VER2_0),
+	DEF_WRITE_MSR(MSR_IA32_APICBASE, X86_TRAP_VE, NO_PRE_COND, VER1_5| VER2_0),
+	DEF_READ_MSR(MSR_TEST_CTRL, X86_TRAP_VE, NO_PRE_COND, VER1_5| VER2_0),
+	DEF_WRITE_MSR(MSR_TEST_CTRL, X86_TRAP_VE, NO_PRE_COND, VER1_5| VER2_0),
+	DEF_READ_MSR(MSR_IA32_TSC_ADJUST, X86_TRAP_VE, NO_PRE_COND, VER1_5| VER2_0),
+	DEF_WRITE_MSR(MSR_IA32_TSC_ADJUST, X86_TRAP_VE, NO_PRE_COND, VER1_5| VER2_0),
 	DEF_READ_MSR(MSR_IA32_TSC, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0),
 	DEF_WRITE_MSR(MSR_IA32_TSC, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0),
 	DEF_READ_MSR(MSR_IA32_SPEC_CTRL, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0),
@@ -314,8 +314,8 @@ struct test_msr msr_cases[] = {
 	DEF_WRITE_MSR(MSR_IA32_CR_PAT, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0),
 	DEF_READ_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x8, VER1_0 | VER1_5),
 	DEF_WRITE_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x8, VER1_0 | VER1_5),
-	DEF_READ_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x4, VER1_0 | VER1_5),
-	DEF_WRITE_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x4, VER1_0 | VER1_5),
+	DEF_READ_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x4, VER2_0),
+	DEF_WRITE_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x4, VER2_0),
 	DEF_READ_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
 	DEF_WRITE_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),