tdx-compliance: Add a workaround

Due to the limitation of KVM, the number of PMU is not align with the spec. Signed-off-by: Yi Sun <[email protected]>
intel · Feb 26, 2024 · 07acc7c · 07acc7c
1 parent d601018
commit 07acc7c
Showing 1 changed file with 10 additions and 4 deletions.
diff --git a/tdx-compliance/tdx-compliance-msr.h b/tdx-compliance/tdx-compliance-msr.h
@@ -312,10 +312,16 @@ struct test_msr msr_cases[] = {
 	DEF_WRITE_MSR(MSR_SLAM_ENABLE, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0),
 	DEF_READ_MSR(MSR_IA32_CR_PAT, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0),
 	DEF_WRITE_MSR(MSR_IA32_CR_PAT, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0),
-	DEF_READ_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x8, VER1_0 | VER1_5),
-	DEF_WRITE_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x8, VER1_0 | VER1_5),
-	DEF_READ_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x4, VER2_0),
-	DEF_WRITE_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x4, VER2_0),
+
+//Workaround for MSR_CORE_PERF_FIXED_CTR0
+//	DEF_READ_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x8, VER1_0 | VER1_5),
+//	DEF_WRITE_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x8, VER1_0 | VER1_5),
+//	DEF_READ_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x4, VER2_0),
+//	DEF_WRITE_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x4, VER2_0),
+	DEF_READ_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x1, VER1_0 | VER1_5),
+	DEF_WRITE_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x1, VER1_0 | VER1_5),
+	DEF_READ_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x1, VER2_0),
+	DEF_WRITE_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x1, VER2_0),
 	DEF_READ_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
 	DEF_WRITE_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),