Skip to content

Commit

Permalink
Add ARL support
Browse files Browse the repository at this point in the history 
Add ARL support
  • Loading branch information
@matborzyszkowski @igcbot
matborzyszkowski authored and igcbot committed Sep 14, 2023
1 parent 9900809 commit b7e0f3e
Show file tree
Hide file tree
Showing 9 changed files with 44 additions and 16 deletions.
1 change: 1 addition & 0 deletions IGC/AdaptorCommon/RayTracing/RTBuilder.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1437,6 +1437,7 @@ Value* RTBuilder::getSyncStackID()
auto& PlatformInfo = Ctx.platform.getPlatformInfo();

if (PlatformInfo.eProductFamily == IGFX_DG2 ||
PlatformInfo.eProductFamily == IGFX_ARROWLAKE ||
PlatformInfo.eProductFamily == IGFX_METEORLAKE)
{
return _getSyncStackID_Xe(VALUE_NAME("SyncStackID"));
Expand Down
4 changes: 4 additions & 0 deletions IGC/Compiler/CISACodeGen/CISABuilder.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3115,6 +3115,10 @@ namespace IGC
{
return Xe_MTL;
}
else if (platform->getPlatformInfo().eProductFamily == IGFX_ARROWLAKE)
{
return Xe_ARL;
}
else if (platform->getPlatformInfo().eProductFamily == IGFX_PVC)
{
if (platform->getPlatformInfo().usRevId >= REVISION_B)
Expand Down
7 changes: 4 additions & 3 deletions IGC/Compiler/CISACodeGen/EmitVISAPass.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15223,7 +15223,7 @@ void EmitPass::emitMemoryFence(llvm::Instruction* inst)
if (CLCtx->m_InternalOptions.StoreCacheDefault != -1)
L1_Evict = static_cast<LSC_L1_L3_CC>(CLCtx->m_InternalOptions.StoreCacheDefault) == LSC_L1IAR_WB_L3C_WB;
}
// Change the scope from `GPU` to `Tile` on single-tile platforms to avoid L3 flush on DG2 and MTL
// Change the scope from `GPU` to `Tile` on single-tile platforms to avoid L3 flush on DG2 and MTL and ARL.
if (scope == LSC_SCOPE_GPU &&
!m_currShader->m_Platform->hasMultiTile() &&
m_currShader->m_Platform->hasL3FlushOnGPUScopeInvalidate() &&
Expand Down Expand Up @@ -21005,7 +21005,8 @@ EmitPass::LscMessageFragmentInfo EmitPass::checkForLscMessageFragmentation(
const int dataSizeMemBytes = toBytesMem(dataSize);
// const int dataElemsCount = toCount(dataElems);
const bool isDg2 = (m_currShader->m_Platform->getPlatformInfo().eProductFamily == IGFX_DG2
|| m_currShader->m_Platform->getPlatformInfo().eProductFamily == IGFX_METEORLAKE);
|| m_currShader->m_Platform->getPlatformInfo().eProductFamily == IGFX_METEORLAKE
|| m_currShader->m_Platform->getPlatformInfo().eProductFamily == IGFX_ARROWLAKE);
const bool isPvcPlus = !isDg2;
const int simdElems = numLanes(m_currShader->m_SIMDSize);
bool halfSimdMode =
Expand Down Expand Up @@ -21560,7 +21561,7 @@ void EmitPass::emitLSCFence(llvm::GenIntrinsicInst* inst)
IGC_ASSERT_EXIT_MESSAGE(0, "LSC system scope is available for UGM data-port only.");
}

// Change the scope from `GPU` to `Tile` on single-tile platforms to avoid L3 flush on DG2 and MTL
// Change the scope from `GPU` to `Tile` on single-tile platforms to avoid L3 flush on DG2 and MTL and ARL.
if (scope == LSC_SCOPE_GPU &&
!m_currShader->m_Platform->hasMultiTile() &&
m_currShader->m_Platform->hasL3FlushOnGPUScopeInvalidate() &&
Expand Down
36 changes: 25 additions & 11 deletions IGC/Compiler/CISACodeGen/Platform.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,8 @@ bool hasNoInt64Inst() const {
m_platformInfo.eProductFamily == IGFX_ALDERLAKE_N ||
m_platformInfo.eProductFamily == IGFX_DG1 ||
m_platformInfo.eProductFamily == IGFX_DG2 ||
m_platformInfo.eProductFamily == IGFX_METEORLAKE;
m_platformInfo.eProductFamily == IGFX_METEORLAKE ||
m_platformInfo.eProductFamily == IGFX_ARROWLAKE;
}

public:
Expand Down Expand Up @@ -698,7 +699,8 @@ bool hasHalfSIMDLSC() const
GFX_IS_DG2_G12_CONFIG(m_platformInfo.usDeviceID) ||
// false for PVC XL A0 RevID==0x0, true from PVC XT A0 RevID==0x3==REVISION_B
(m_platformInfo.eProductFamily == IGFX_PVC && m_platformInfo.usRevId >= REVISION_B) ||
m_platformInfo.eProductFamily == IGFX_METEORLAKE;
m_platformInfo.eProductFamily == IGFX_METEORLAKE ||
m_platformInfo.eProductFamily == IGFX_ARROWLAKE;
}

bool NeedsLSCFenceUGMBeforeEOT() const
Expand Down Expand Up @@ -799,7 +801,8 @@ bool supports3DAndCubeSampleD() const
return (
m_platformInfo.eProductFamily != IGFX_XE_HP_SDV &&
m_platformInfo.eProductFamily != IGFX_DG2 &&
m_platformInfo.eProductFamily != IGFX_METEORLAKE
m_platformInfo.eProductFamily != IGFX_METEORLAKE &&
m_platformInfo.eProductFamily != IGFX_ARROWLAKE
) ||
IGC_IS_FLAG_DISABLED(EnableSampleDEmulation);
}
Expand Down Expand Up @@ -850,7 +853,8 @@ uint32_t getMaxLSCBlockMsgSize(bool isD64 = true) const
bool hasURBFence() const
{
return m_platformInfo.eProductFamily == IGFX_DG2 ||
m_platformInfo.eProductFamily == IGFX_METEORLAKE;
m_platformInfo.eProductFamily == IGFX_METEORLAKE ||
m_platformInfo.eProductFamily == IGFX_ARROWLAKE;
}

bool hasMultiTile() const
Expand All @@ -862,8 +866,10 @@ bool hasMultiTile() const
// UGM LSC fence with GPU scope triggers L3 flush
bool hasL3FlushOnGPUScopeInvalidate() const
{
return m_platformInfo.eProductFamily == IGFX_METEORLAKE ||
m_platformInfo.eProductFamily == IGFX_DG2;
return
m_platformInfo.eProductFamily == IGFX_ARROWLAKE ||
m_platformInfo.eProductFamily == IGFX_METEORLAKE ||
m_platformInfo.eProductFamily == IGFX_DG2;
}

bool L3CacheCoherentCrossTiles() const {
Expand All @@ -874,6 +880,7 @@ bool AllowFenceOpt() const
{
return ((m_platformInfo.eProductFamily == IGFX_DG2
|| m_platformInfo.eProductFamily == IGFX_METEORLAKE
|| m_platformInfo.eProductFamily == IGFX_ARROWLAKE
|| m_platformInfo.eProductFamily == IGFX_PVC) &&
IGC_IS_FLAG_ENABLED(EnablePlatformFenceOpt));
}
Expand Down Expand Up @@ -952,6 +959,7 @@ bool typedReadSupportsAllRenderableFormats() const
(m_platformInfo.eProductFamily == IGFX_DG2 && isDG2G11Config && isChildOfDG2B0) ||
(m_platformInfo.eProductFamily == IGFX_DG2 && isDG2G12Config) ||
(m_platformInfo.eProductFamily == IGFX_METEORLAKE) ||
(m_platformInfo.eProductFamily == IGFX_ARROWLAKE) ||
(m_platformInfo.eRenderCoreFamily == IGFX_XE_HPC_CORE))
{
return IGC_IS_FLAG_DISABLED(ForceFormatConversionDG2Plus);
Expand All @@ -962,8 +970,9 @@ bool typedReadSupportsAllRenderableFormats() const

bool needsWAForThreadsUtilization() const
{
return m_platformInfo.eProductFamily == IGFX_DG2 ||
m_platformInfo.eProductFamily == IGFX_METEORLAKE;
return (m_platformInfo.eProductFamily == IGFX_DG2 ||
m_platformInfo.eProductFamily == IGFX_METEORLAKE ||
m_platformInfo.eProductFamily == IGFX_ARROWLAKE);
}

bool supportDualSimd8PS() const
Expand Down Expand Up @@ -1124,12 +1133,14 @@ bool hasCorrectlyRoundedMacros() const {
m_platformInfo.eProductFamily != IGFX_ALDERLAKE_P &&
m_platformInfo.eProductFamily != IGFX_ALDERLAKE_N &&
m_platformInfo.eProductFamily != IGFX_DG2 &&
m_platformInfo.eProductFamily != IGFX_METEORLAKE);
m_platformInfo.eProductFamily != IGFX_METEORLAKE) &&
m_platformInfo.eProductFamily != IGFX_ARROWLAKE;
}

// Has 64bit support but use 32bit for perf reasons
bool preferFP32IntDivRemEmu() const {
return m_platformInfo.eProductFamily == IGFX_METEORLAKE;
return m_platformInfo.eProductFamily == IGFX_METEORLAKE ||
m_platformInfo.eProductFamily == IGFX_ARROWLAKE;
}

// Platforms that haven't HW support for FP64 operations
Expand Down Expand Up @@ -1204,6 +1215,7 @@ bool canFuseTypedWrite() const
bool isDG2G11Config = GFX_IS_DG2_G11_CONFIG(m_platformInfo.usDeviceID);
bool isDG2G12Config = GFX_IS_DG2_G12_CONFIG(m_platformInfo.usDeviceID);
bool canFuse = (m_platformInfo.eProductFamily == IGFX_METEORLAKE) ||
(m_platformInfo.eProductFamily == IGFX_ARROWLAKE) ||
(m_platformInfo.eProductFamily == IGFX_DG2 && isChildOfDG2C0) ||
(m_platformInfo.eProductFamily == IGFX_DG2 && isDG2G11Config && isChildOfDG2B0) ||
(m_platformInfo.eProductFamily == IGFX_DG2 && isDG2G12Config);
Expand Down Expand Up @@ -1334,7 +1346,8 @@ bool supportSystemFence() const
{
return hasLSC()
&& m_platformInfo.eProductFamily != IGFX_DG2
&& m_platformInfo.eProductFamily != IGFX_METEORLAKE;
&& m_platformInfo.eProductFamily != IGFX_METEORLAKE
&& m_platformInfo.eProductFamily != IGFX_ARROWLAKE;
}


Expand Down Expand Up @@ -1406,6 +1419,7 @@ bool noNativeDwordMulSupport() const
m_platformInfo.eProductFamily == IGFX_GEMINILAKE ||
m_platformInfo.eProductFamily == IGFX_DG2 ||
m_platformInfo.eProductFamily == IGFX_METEORLAKE ||
m_platformInfo.eProductFamily == IGFX_ARROWLAKE ||
GetPlatformFamily() == IGFX_GEN11_CORE ||
GetPlatformFamily() == IGFX_GEN12LP_CORE;
}
Expand Down
1 change: 1 addition & 0 deletions IGC/Compiler/Optimizer/OpenCLPasses/LSCFuncs/LSCFuncsResolution.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -220,6 +220,7 @@ bool LSCFuncsResolution::runOnFunction(Function &F)
{
case IGFX_DG2:
case IGFX_METEORLAKE:
case IGFX_ARROWLAKE:
defaultSimdSize = 16;
break;
default:
Expand Down
4 changes: 4 additions & 0 deletions IGC/common/ShaderOverride.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -146,6 +146,10 @@ iga_gen_t GetIGAPlatform(PLATFORM const & platform)
{
return IGA_XE_HPG;
}
else if (ProductFamily == IGFX_ARROWLAKE)
{
return IGA_XE_HPG;
}
else if (ProductFamily == IGFX_PVC)
{
return IGA_XE_HPC;
Expand Down
5 changes: 3 additions & 2 deletions IGC/common/SystemThread.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -144,7 +144,7 @@ struct XeHPCDebugSurfaceLayout
static constexpr size_t DBG_REG_ELEMENTS = 2;
static constexpr size_t DBG_REG_ELEMENT_SIZE = 4;
static constexpr size_t DBG_REG_ALIGN = 24;

uint8_t grf[GR_COUNT * GR_ELEMENTS * GR_ELEMENT_SIZE + GR_ALIGN];
uint8_t a0[A0_COUNT * A0_ELEMENTS * A0_ELEMENT_SIZE + A0_ALIGN];
uint8_t f[F_COUNT * F_ELEMENTS * F_ELEMENT_SIZE + F_ALIGN];
Expand Down Expand Up @@ -733,7 +733,6 @@ bool CSystemThread::CreateSystemThreadKernel(
return success;
}


void CSystemThread::DeleteSystemThreadKernel(
USC::SSystemThreadKernelOutput* &pSystemThreadKernelOutput )
{
Expand Down Expand Up @@ -971,6 +970,7 @@ CGenSystemInstructionKernelProgram* CGenSystemInstructionKernelProgram::Create(
break;
case IGFX_DG2:
case IGFX_METEORLAKE:
case IGFX_ARROWLAKE:
SIPIndex = bindlessMode ? XE_HPG_CSR_DEBUG_BINDLESS : XE_HPG_CSR_DEBUG;
break;
// No support for Bindful mode for PVC.
Expand Down Expand Up @@ -1002,6 +1002,7 @@ CGenSystemInstructionKernelProgram* CGenSystemInstructionKernelProgram::Create(
case IGFX_DG2:
case IGFX_PVC:
case IGFX_METEORLAKE:
case IGFX_ARROWLAKE:

default:
break;
Expand Down
1 change: 1 addition & 0 deletions inc/common/igfxfmid.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ typedef enum {
IGFX_DG2 = 1270, // aka - ACM/Alchemist
IGFX_PVC = 1271,
IGFX_METEORLAKE = 1272,
IGFX_ARROWLAKE = 1273,
IGFX_MAX_PRODUCT,


Expand Down
1 change: 1 addition & 0 deletions visa/include/visa_igc_common_header.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -490,6 +490,7 @@ typedef enum {
Xe_XeHPSDV,
Xe_DG2,
Xe_MTL,
Xe_ARL,
Xe_PVC,
Xe_PVCXT,
ALL
Expand Down

0 comments on commit b7e0f3e

Please sign in to comment.