Use new PrefetchReserved[3-7] instead of reserved-nop

icedland · May 26, 2020 · a8ea37c · a8ea37c
1 parent c62f977
commit a8ea37c
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Showing 55 changed files with 538 additions and 42 deletions.
diff --git a/src/UnitTests/Intel/Decoder/DecoderTest16.txt b/src/UnitTests/Intel/Decoder/DecoderTest16.txt
@@ -2738,11 +2738,11 @@ F3 0F09, Wbnoinvd, Wbnoinvd, 0,
 
 0F0D CE, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=r;si op1=r;cx resnop
 0F0D 18, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;bx resnop
-0F0D 18, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;bx
-0F0D 20, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;sp
-0F0D 28, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;bp
-0F0D 30, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;si
-0F0D 38, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;di
+0F0D 18, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;bx resnop
+0F0D 20, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;sp resnop
+0F0D 28, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;bp resnop
+0F0D 30, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;si resnop
+0F0D 38, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;di resnop
 
 66 0F0D CE, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=r;esi op1=r;ecx resnop
 66 0F0D 18, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt32 op1=r;ebx resnop
@@ -2753,6 +2753,16 @@ F3 0F09, Wbnoinvd, Wbnoinvd, 0,
 
 0F0D 10, Prefetchwt1_m8, Prefetchwt1, 1, op0=m;ds;bx;si;1;0;0;UInt8
 
+0F0D 18, PrefetchReserved3_m8, Prefetchw, 1, op0=m;ds;bx;si;1;0;0;UInt8
+
+0F0D 20, PrefetchReserved4_m8, Prefetch, 1, op0=m;ds;bx;si;1;0;0;UInt8
+
+0F0D 28, PrefetchReserved5_m8, Prefetch, 1, op0=m;ds;bx;si;1;0;0;UInt8
+
+0F0D 30, PrefetchReserved6_m8, Prefetch, 1, op0=m;ds;bx;si;1;0;0;UInt8
+
+0F0D 38, PrefetchReserved7_m8, Prefetch, 1, op0=m;ds;bx;si;1;0;0;UInt8
+
 0F0E, Femms, Femms, 0,
 
 0F10 CE, Umov_rm8_r8, Umov, 2, op0=r;dh op1=r;cl umov

diff --git a/src/UnitTests/Intel/Decoder/DecoderTest32.txt b/src/UnitTests/Intel/Decoder/DecoderTest32.txt
@@ -2741,18 +2741,28 @@ F3 0F09, Wbnoinvd, Wbnoinvd, 0,
 
 0F0D CE, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=r;esi op1=r;ecx resnop
 0F0D 18, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;ebx resnop
-0F0D 18, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;ebx
-0F0D 20, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;esp
-0F0D 28, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;ebp
-0F0D 30, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;esi
-0F0D 38, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;edi
+0F0D 18, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;ebx resnop
+0F0D 20, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;esp resnop
+0F0D 28, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;ebp resnop
+0F0D 30, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;esi resnop
+0F0D 38, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;edi resnop
 
 0F0D 00, Prefetch_m8, Prefetch, 1, op0=m;ds;eax;;1;0;0;UInt8
 
 0F0D 08, Prefetchw_m8, Prefetchw, 1, op0=m;ds;eax;;1;0;0;UInt8
 
 0F0D 10, Prefetchwt1_m8, Prefetchwt1, 1, op0=m;ds;eax;;1;0;0;UInt8
 
+0F0D 18, PrefetchReserved3_m8, Prefetchw, 1, op0=m;ds;eax;;1;0;0;UInt8
+
+0F0D 20, PrefetchReserved4_m8, Prefetch, 1, op0=m;ds;eax;;1;0;0;UInt8
+
+0F0D 28, PrefetchReserved5_m8, Prefetch, 1, op0=m;ds;eax;;1;0;0;UInt8
+
+0F0D 30, PrefetchReserved6_m8, Prefetch, 1, op0=m;ds;eax;;1;0;0;UInt8
+
+0F0D 38, PrefetchReserved7_m8, Prefetch, 1, op0=m;ds;eax;;1;0;0;UInt8
+
 0F0E, Femms, Femms, 0,
 
 0F10 CE, Umov_rm8_r8, Umov, 2, op0=r;dh op1=r;cl umov

diff --git a/src/UnitTests/Intel/Decoder/DecoderTest64.txt b/src/UnitTests/Intel/Decoder/DecoderTest64.txt
@@ -5336,11 +5336,11 @@ F3 4F 0F09, Wbnoinvd, Wbnoinvd, 0, enc=F30F09
 41 0F0D D9, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=r;r9d op1=r;ebx resnop
 44 0F0D EC, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=r;esp op1=r;r13d resnop
 0F0D 18, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;ebx resnop
-0F0D 18, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;ebx
-0F0D 20, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;esp
-0F0D 28, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;ebp
-0F0D 30, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;esi
-0F0D 38, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;edi
+0F0D 18, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;ebx resnop
+0F0D 20, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;esp resnop
+0F0D 28, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;ebp resnop
+0F0D 30, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;esi resnop
+0F0D 38, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;edi resnop
 42 0F0D CE, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=r;esi op1=r;ecx resnop enc=0F0DCE
 
 48 0F0D CE, ReservedNop_rm64_r64_0F0D, ReservedNop, 2, op0=r;rsi op1=r;rcx resnop
@@ -5361,6 +5361,21 @@ F3 4F 0F09, Wbnoinvd, Wbnoinvd, 0, enc=F30F09
 0F0D 10, Prefetchwt1_m8, Prefetchwt1, 1, op0=m;ds;rax;;1;0;0;UInt8
 44 0F0D 10, Prefetchwt1_m8, Prefetchwt1, 1, op0=m;ds;rax;;1;0;0;UInt8 enc=0F0D10
 
+0F0D 18, PrefetchReserved3_m8, Prefetchw, 1, op0=m;ds;rax;;1;0;0;UInt8
+44 0F0D 18, PrefetchReserved3_m8, Prefetchw, 1, op0=m;ds;rax;;1;0;0;UInt8 enc=0F0D18
+
+0F0D 20, PrefetchReserved4_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8
+44 0F0D 20, PrefetchReserved4_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8 enc=0F0D20
+
+0F0D 28, PrefetchReserved5_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8
+44 0F0D 28, PrefetchReserved5_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8 enc=0F0D28
+
+0F0D 30, PrefetchReserved6_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8
+44 0F0D 30, PrefetchReserved6_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8 enc=0F0D30
+
+0F0D 38, PrefetchReserved7_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8
+44 0F0D 38, PrefetchReserved7_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8 enc=0F0D38
+
 0F0E, Femms, Femms, 0,
 4F 0F0E, Femms, Femms, 0, enc=0F0E
 

diff --git a/src/UnitTests/Intel/Encoder/OpCodeInfos.txt b/src/UnitTests/Intel/Encoder/OpCodeInfos.txt
@@ -907,6 +907,11 @@ ReservedNop_rm64_r64_0F0D, legacy, , 0F, 0D, REX.W 0F 0D /r, RESERVEDNOP r/m64|
 Prefetch_m8, legacy, , 0F, 0D, 0F 0D /0, PREFETCH m8, g=0 16b 32b 64b op=mem
 Prefetchw_m8, legacy, , 0F, 0D, 0F 0D /1, PREFETCHW m8, g=1 16b 32b 64b op=mem
 Prefetchwt1_m8, legacy, , 0F, 0D, 0F 0D /2, PREFETCHWT1 m8, g=2 16b 32b 64b op=mem
+PrefetchReserved3_m8, legacy, , 0F, 0D, 0F 0D /3, PREFETCHW m8, g=3 16b 32b 64b op=mem
+PrefetchReserved4_m8, legacy, , 0F, 0D, 0F 0D /4, PREFETCH m8, g=4 16b 32b 64b op=mem
+PrefetchReserved5_m8, legacy, , 0F, 0D, 0F 0D /5, PREFETCH m8, g=5 16b 32b 64b op=mem
+PrefetchReserved6_m8, legacy, , 0F, 0D, 0F 0D /6, PREFETCH m8, g=6 16b 32b 64b op=mem
+PrefetchReserved7_m8, legacy, , 0F, 0D, 0F 0D /7, PREFETCH m8, g=7 16b 32b 64b op=mem
 Femms, legacy, , 0F, 0E, 0F 0E, FEMMS, 16b 32b 64b
 Umov_rm8_r8, legacy, , 0F, 10, 0F 10 /r, UMOV r/m8| r8, 16b 32b op=r8_or_mem;r8_reg
 Umov_rm16_r16, legacy, , 0F, 11, o16 0F 11 /r, UMOV r/m16| r16, 16b 32b o16 op=r16_or_mem;r16_reg

diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 addr32 invlpgb
 invlpgb
 tlbsync
+prefetchw (rax)
+prefetch (rax)
+prefetch (rax)
+prefetch (rax)
+prefetch (rax)
diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 addr32 invlpgb
 invlpgb
 tlbsync
+prefetchw (%rax)
+prefetch (%rax)
+prefetch (%rax)
+prefetch (%rax)
+prefetch (%rax)
diff --git a/src/UnitTests/Intel/Formatter/InstructionInfos64.txt b/src/UnitTests/Intel/Formatter/InstructionInfos64.txt
@@ -8358,3 +8358,8 @@ F2 0F 01 E9, Xresldtrk
 67 0F 01 FE, Invlpgbd
 0F 01 FE, Invlpgbq
 0F 01 FF, Tlbsync
+0F0D 18, PrefetchReserved3_m8
+0F0D 20, PrefetchReserved4_m8
+0F0D 28, PrefetchReserved5_m8
+0F0D 30, PrefetchReserved6_m8
+0F0D 38, PrefetchReserved7_m8
diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 invlpgb eax
 invlpgb rax
 tlbsync
+prefetchw byte ptr [rax]
+prefetch_reserved byte ptr [rax]
+prefetch_reserved byte ptr [rax]
+prefetch_reserved byte ptr [rax]
+prefetch_reserved byte ptr [rax]
diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 invlpgb eax
 invlpgb rax
 tlbsync
+prefetchw [rax]
+prefetch_reserved [rax]
+prefetch_reserved [rax]
+prefetch_reserved [rax]
+prefetch_reserved [rax]
diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 invlpgb eax
 invlpgb rax
 tlbsync
+prefetchw [rax]
+prefetch_reserved [rax]
+prefetch_reserved [rax]
+prefetch_reserved [rax]
+prefetch_reserved [rax]
diff --git a/src/UnitTests/Intel/Formatter/Masm/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Masm/Test64_MemAlways.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 invlpgb
 invlpgb
 tlbsync
+prefetchw byte ptr [rax]
+prefetch byte ptr [rax]
+prefetch byte ptr [rax]
+prefetch byte ptr [rax]
+prefetch byte ptr [rax]
diff --git a/src/UnitTests/Intel/Formatter/Masm/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Masm/Test64_MemDefault.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 invlpgb
 invlpgb
 tlbsync
+prefetchw [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
diff --git a/src/UnitTests/Intel/Formatter/Masm/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Masm/Test64_MemMinimum.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 invlpgb
 invlpgb
 tlbsync
+prefetchw [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 a32 invlpgb
 invlpgb
 tlbsync
+prefetchw [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 a32 invlpgb
 invlpgb
 tlbsync
+prefetchw [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 a32 invlpgb
 invlpgb
 tlbsync
+prefetchw [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
diff --git a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_32.txt b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_32.txt
@@ -1555,6 +1555,16 @@ C5ED FB CA, VEX_Vpsubq_ymm_ymm_ymmm256, VEX, AVX2, pm op0=w op1=n op2=n w=vmm1
 0F0D 08, Prefetchw_m8, Legacy, PREFETCHW, op0=nma r=eax;ds
 # prefetchwt1 [eax]
 0F0D 10, Prefetchwt1_m8, Legacy, PREFETCHWT1, op0=nma r=eax;ds
+# prefetchw [eax]
+0F0D 18, PrefetchReserved3_m8, Legacy, PREFETCHW, op0=nma r=eax;ds
+# prefetch [eax]
+0F0D 20, PrefetchReserved4_m8, Legacy, PREFETCHW, op0=nma r=eax;ds
+# prefetch [eax]
+0F0D 28, PrefetchReserved5_m8, Legacy, PREFETCHW, op0=nma r=eax;ds
+# prefetch [eax]
+0F0D 30, PrefetchReserved6_m8, Legacy, PREFETCHW, op0=nma r=eax;ds
+# prefetch [eax]
+0F0D 38, PrefetchReserved7_m8, Legacy, PREFETCHW, op0=nma r=eax;ds
 # prefetchnta [eax]
 0F18 00, Prefetchnta_m8, Legacy, SSE, op0=nma r=eax;ds
 # prefetcht0 [eax]

diff --git a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt
@@ -2945,10 +2945,22 @@ FF 30, Push_rm64, Legacy, X64, op0=r rw=xsp r=rax rm=ds:rax;UInt64 wm=ss:xsp+0xF
 0F09, Wbinvd, Legacy, INTEL486, priv
 # ud2
 0F0B, Ud2, Legacy, INTEL286, flow=Exception
+# prefetch [rax]
+0F0D 00, Prefetch_m8, Legacy, PREFETCHW, op0=nma r=rax
 # prefetchw [rax]
 0F0D 08, Prefetchw_m8, Legacy, PREFETCHW, op0=nma r=rax
 # prefetchwt1 [rax]
 0F0D 10, Prefetchwt1_m8, Legacy, PREFETCHWT1, op0=nma r=rax
+# prefetchw [rax]
+0F0D 18, PrefetchReserved3_m8, Legacy, PREFETCHW, op0=nma r=rax
+# prefetch [rax]
+0F0D 20, PrefetchReserved4_m8, Legacy, PREFETCHW, op0=nma r=rax
+# prefetch [rax]
+0F0D 28, PrefetchReserved5_m8, Legacy, PREFETCHW, op0=nma r=rax
+# prefetch [rax]
+0F0D 30, PrefetchReserved6_m8, Legacy, PREFETCHW, op0=nma r=rax
+# prefetch [rax]
+0F0D 38, PrefetchReserved7_m8, Legacy, PREFETCHW, op0=nma r=rax
 # movups xmm1,xmm5
 0F10 CD, Movups_xmm_xmmm128, Legacy, SSE, op0=w op1=r w=xmm1 r=xmm5
 # movups xmm1,[rax]
@@ -16485,8 +16497,6 @@ F3 0F01 FA, Mcommit, Legacy, MCOMMIT, fw=c fc=aopsz
 0F01 FC, Clzeroq, Legacy, CLZERO, r=rax
 # rdpru
 0F01 FD, Rdpru, Legacy, RDPRU, fw=c fc=aopsz r=ecx w=rax;rdx
-# prefetch [rax]
-0F0D 00, Prefetch_m8, Legacy, PREFETCHW, op0=nma r=rax
 # femms
 0F0E, Femms, Legacy, D3NOW,
 # movntss dword ptr [rax],xmm1

diff --git a/src/csharp/Intel/Generator/Assembler/AssemblerSyntaxGenerator.cs b/src/csharp/Intel/Generator/Assembler/AssemblerSyntaxGenerator.cs
@@ -151,6 +151,12 @@ protected AssemblerSyntaxGenerator(GenTypes genTypes) {
 
 				Code.Popw_CS,
 
+				Code.PrefetchReserved3_m8,
+				Code.PrefetchReserved4_m8,
+				Code.PrefetchReserved5_m8,
+				Code.PrefetchReserved6_m8,
+				Code.PrefetchReserved7_m8,
+
 				// The following are implemented manually
 				Code.Call_ptr1616,
 				Code.Call_ptr1632,

diff --git a/src/csharp/Intel/Generator/Decoder/DecoderTable_Legacy.cs b/src/csharp/Intel/Generator/Decoder/DecoderTable_Legacy.cs
@@ -1864,11 +1864,11 @@ public static (string name, object?[] handlers)[] CreateHandlers(GenTypes genTyp
 					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.Prefetch_m8)] },
 					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.Prefetchw_m8)] },
 					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.Prefetchwt1_m8)] },
-					"reservedNop_0F0D",
-					"reservedNop_0F0D",
-					"reservedNop_0F0D",
-					"reservedNop_0F0D",
-					"reservedNop_0F0D",
+					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.PrefetchReserved3_m8)] },
+					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.PrefetchReserved4_m8)] },
+					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.PrefetchReserved5_m8)] },
+					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.PrefetchReserved6_m8)] },
+					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.PrefetchReserved7_m8)] },
 				}),
 				("grp0F0D", new object[] { legacyEnum[nameof(OpCodeHandlerKind.RM)],
 					"reservedNop_0F0D",

diff --git a/src/csharp/Intel/Generator/Enums/Code.cs b/src/csharp/Intel/Generator/Enums/Code.cs
@@ -4247,6 +4247,11 @@ enum Code {
 		Invlpgbd,
 		Invlpgbq,
 		Tlbsync,
+		PrefetchReserved3_m8,
+		PrefetchReserved4_m8,
+		PrefetchReserved5_m8,
+		PrefetchReserved6_m8,
+		PrefetchReserved7_m8,
 	}
 
 	[TypeGen(TypeGenOrders.CreatedInstructions)]

diff --git a/src/csharp/Intel/Generator/Formatters/Gas/CtorInfosData.cs b/src/csharp/Intel/Generator/Formatters/Gas/CtorInfosData.cs
@@ -4252,6 +4252,11 @@ public static object[][] GetData(GenTypes genTypes) {
 				new object[] { ctorKind[nameof(CtorKind.asz)], code[nameof(Code.Invlpgbd)], "invlpgb", 32 },
 				new object[] { ctorKind[nameof(CtorKind.asz)], code[nameof(Code.Invlpgbq)], "invlpgb", 64 },
 				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Tlbsync)], "tlbsync" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved3_m8)], "prefetchw" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved4_m8)], "prefetch" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved5_m8)], "prefetch" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved6_m8)], "prefetch" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved7_m8)], "prefetch" },
 			});
 		}
 	}

diff --git a/src/csharp/Intel/Generator/Formatters/Intel/CtorInfosData.cs b/src/csharp/Intel/Generator/Formatters/Intel/CtorInfosData.cs
@@ -4252,6 +4252,11 @@ public static object[][] GetData(GenTypes genTypes) {
 				new object[] { ctorKind[nameof(CtorKind.reg)], code[nameof(Code.Invlpgbd)], "invlpgb", register[nameof(Register.EAX)] },
 				new object[] { ctorKind[nameof(CtorKind.reg)], code[nameof(Code.Invlpgbq)], "invlpgb", register[nameof(Register.RAX)] },
 				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Tlbsync)], "tlbsync" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved3_m8)], "prefetchw" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved4_m8)], "prefetch_reserved" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved5_m8)], "prefetch_reserved" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved6_m8)], "prefetch_reserved" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved7_m8)], "prefetch_reserved" },
 			});
 		}
 	}

diff --git a/src/csharp/Intel/Generator/Formatters/Masm/CtorInfosData.cs b/src/csharp/Intel/Generator/Formatters/Masm/CtorInfosData.cs
@@ -4252,6 +4252,11 @@ public static object[][] GetData(GenTypes genTypes) {
 				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Invlpgbd)], "invlpgb" },
 				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Invlpgbq)], "invlpgb" },
 				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Tlbsync)], "tlbsync" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved3_m8)], "prefetchw" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved4_m8)], "prefetch" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved5_m8)], "prefetch" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved6_m8)], "prefetch" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved7_m8)], "prefetch" },
 			});
 		}
 	}

diff --git a/src/csharp/Intel/Generator/Formatters/Nasm/CtorInfosData.cs b/src/csharp/Intel/Generator/Formatters/Nasm/CtorInfosData.cs
@@ -4254,6 +4254,11 @@ public static object[][] GetData(GenTypes genTypes) {
 				new object[] { ctorKind[nameof(CtorKind.asz)], code[nameof(Code.Invlpgbd)], "invlpgb", 32 },
 				new object[] { ctorKind[nameof(CtorKind.asz)], code[nameof(Code.Invlpgbq)], "invlpgb", 64 },
 				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Tlbsync)], "tlbsync" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.PrefetchReserved3_m8)], "prefetchw", instrOpInfoFlags[nameof(InstrOpInfoFlags.MemSize_Nothing)] },
+				new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.PrefetchReserved4_m8)], "prefetch", instrOpInfoFlags[nameof(InstrOpInfoFlags.MemSize_Nothing)] },
+				new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.PrefetchReserved5_m8)], "prefetch", instrOpInfoFlags[nameof(InstrOpInfoFlags.MemSize_Nothing)] },
+				new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.PrefetchReserved6_m8)], "prefetch", instrOpInfoFlags[nameof(InstrOpInfoFlags.MemSize_Nothing)] },
+				new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.PrefetchReserved7_m8)], "prefetch", instrOpInfoFlags[nameof(InstrOpInfoFlags.MemSize_Nothing)] },
 			});
 		}
 	}