Don't print data16/32/64

icedland · May 26, 2020 · 3553baf · 3553baf
1 parent 8c10379
commit 3553baf
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Showing 52 changed files with 90 additions and 341 deletions.
diff --git a/src/UnitTests/Intel/Formatter/Gas/Test16_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test16_ForceSuffix.txt
@@ -244,7 +244,7 @@ scasw (di), ax
 scasl (edi), eax
 scasl (di), eax
 xbegin 0x0000254e
-data32 xbegin 0x34132551
+xbegin 0x34132551
 enterw $-0x5aa6, $-0x5a
 leavew
 lretw $-0x5aa6

diff --git a/src/UnitTests/Intel/Formatter/Gas/Test16_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test16_NoSuffix.txt
@@ -244,7 +244,7 @@ scas (%di),%ax
 scas (%edi),%eax
 scas (%di),%eax
 xbegin 0x0000254e
-data32 xbegin 0x34132551
+xbegin 0x34132551
 enter $0xa55a,$0xa6
 leave
 lret $0xa55a

diff --git a/src/UnitTests/Intel/Formatter/Gas/Test32_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test32_ForceSuffix.txt
@@ -310,7 +310,7 @@ scasw (di), ax
 scasw (edi), ax
 scasl (di), eax
 scasl (edi), eax
-data16 xbegin 0x7fffa54f
+xbegin 0x7fffa54f
 xbegin 0xb412a550
 enterw $-0x5aa6, $-0x5a
 leavew

diff --git a/src/UnitTests/Intel/Formatter/Gas/Test32_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test32_NoSuffix.txt
@@ -310,7 +310,7 @@ scas (%di),%ax
 scas (%edi),%ax
 scas (%di),%eax
 scas (%edi),%eax
-data16 xbegin 0x7fffa54f
+xbegin 0x7fffa54f
 xbegin 0xb412a550
 enterw $0xa55a,$0xa6
 leavew

diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt
@@ -716,7 +716,7 @@ movl $0x3412a55a, ecx
 movl $0x3412a55a, (rax)
 movq $-0x7bed5aa6, rcx
 movq $-0x7bed5aa6, (rax)
-data16 xbegin 0x7fffffffffffa54f
+xbegin 0x7fffffffffffa54f
 xbegin 0x800000003412a550
 xbegin 0x800000003412a551
 enterw $-0x5aa6, $-0x5a

diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt
@@ -716,7 +716,7 @@ mov $0x3412a55a,%ecx
 movl $0x3412a55a,(%rax)
 mov $0xffffffff8412a55a,%rcx
 movq $0xffffffff8412a55a,(%rax)
-data16 xbegin 0x7fffffffffffa54f
+xbegin 0x7fffffffffffa54f
 xbegin 0x800000003412a550
 xbegin 0x800000003412a551
 enterw $0xa55a,$0xa6

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test16_MemAlways.txt b/src/UnitTests/Intel/Formatter/Intel/Test16_MemAlways.txt
@@ -244,7 +244,7 @@ scasw word ptr [di]
 scasd dword ptr [edi]
 scasd dword ptr [di]
 xbegin 0x0000254e
-data32 xbegin 0x34132551
+xbegin 0x34132551
 enter -0x5aa6, -0x5a
 leave
 ret far -0x5aa6

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test16_MemDefault.txt b/src/UnitTests/Intel/Formatter/Intel/Test16_MemDefault.txt
@@ -244,7 +244,7 @@ scasw [di]
 scasd [edi]
 scasd [di]
 xbegin 0x0000254e
-data32 xbegin 0x34132551
+xbegin 0x34132551
 enter 0xa55a,0xa6
 leave
 ret far 0xa55a

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test16_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Intel/Test16_MemMinimum.txt
@@ -244,7 +244,7 @@ scasw [di]
 scasd [edi]
 scasd [di]
 xbegin 0x0000254e
-data32 xbegin 0x34132551
+xbegin 0x34132551
 enter -0x5aa6, -0x5a
 leave
 ret far -0x5aa6

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test32_MemAlways.txt b/src/UnitTests/Intel/Formatter/Intel/Test32_MemAlways.txt
@@ -310,7 +310,7 @@ scasw word ptr [di]
 scasw word ptr [edi]
 scasd dword ptr [di]
 scasd dword ptr [edi]
-data16 xbegin 0x7fffa54f
+xbegin 0x7fffa54f
 xbegin 0xb412a550
 data16 enter -0x5aa6, -0x5a
 data16 leave

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test32_MemDefault.txt b/src/UnitTests/Intel/Formatter/Intel/Test32_MemDefault.txt
@@ -310,7 +310,7 @@ scasw [di]
 scasw [edi]
 scasd [di]
 scasd [edi]
-data16 xbegin 0x7fffa54f
+xbegin 0x7fffa54f
 xbegin 0xb412a550
 data16 enter 0xa55a,0xa6
 data16 leave

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test32_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Intel/Test32_MemMinimum.txt
@@ -310,7 +310,7 @@ scasw [di]
 scasw [edi]
 scasd [di]
 scasd [edi]
-data16 xbegin 0x7fffa54f
+xbegin 0x7fffa54f
 xbegin 0xb412a550
 data16 enter -0x5aa6, -0x5a
 data16 leave

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt
@@ -716,7 +716,7 @@ mov ecx, 0x3412a55a
 mov dword ptr [rax], 0x3412a55a
 mov rcx, -0x7bed5aa6
 mov qword ptr [rax], -0x7bed5aa6
-data16 xbegin 0x7fffffffffffa54f
+xbegin 0x7fffffffffffa54f
 xbegin 0x800000003412a550
 xbegin 0x800000003412a551
 data16 enter -0x5aa6, -0x5a

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt
@@ -716,7 +716,7 @@ mov ecx,0x3412a55a
 mov dword ptr [rax],0x3412a55a
 mov rcx,0xffffffff8412a55a
 mov qword ptr [rax],0xffffffff8412a55a
-data16 xbegin 0x7fffffffffffa54f
+xbegin 0x7fffffffffffa54f
 xbegin 0x800000003412a550
 xbegin 0x800000003412a551
 data16 enter 0xa55a,0xa6

diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt
@@ -716,7 +716,7 @@ mov ecx, 0x3412a55a
 mov dword ptr [rax], 0x3412a55a
 mov rcx, -0x7bed5aa6
 mov qword ptr [rax], -0x7bed5aa6
-data16 xbegin 0x7fffffffffffa54f
+xbegin 0x7fffffffffffa54f
 xbegin 0x800000003412a550
 xbegin 0x800000003412a551
 data16 enter -0x5aa6, -0x5a

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test16_MemAlways.txt b/src/UnitTests/Intel/Formatter/Nasm/Test16_MemAlways.txt
@@ -244,7 +244,7 @@ scasw
 a32 scasd
 scasd
 xbegin 0x0000254e
-xbegin dword 0x34132551
+xbegin 0x34132551
 enter -0x5aa6, -0x5a
 leave
 retf -0x5aa6

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test16_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Nasm/Test16_MemMinimum.txt
@@ -244,7 +244,7 @@ scasw
 a32 scasd
 scasd
 xbegin 0x0000254e
-xbegin dword 0x34132551
+xbegin 0x34132551
 enter -0x5aa6, -0x5a
 leave
 retf -0x5aa6

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test32_MemAlways.txt b/src/UnitTests/Intel/Formatter/Nasm/Test32_MemAlways.txt
@@ -310,7 +310,7 @@ a16 scasw
 scasw
 a16 scasd
 scasd
-xbegin word 0x7fffa54f
+xbegin 0x7fffa54f
 xbegin 0xb412a550
 o16 enter -0x5aa6, -0x5a
 o16 leave

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test32_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Nasm/Test32_MemMinimum.txt
@@ -310,7 +310,7 @@ a16 scasw
 scasw
 a16 scasd
 scasd
-xbegin word 0x7fffa54f
+xbegin 0x7fffa54f
 xbegin 0xb412a550
 o16 enter -0x5aa6, -0x5a
 o16 leave

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt
@@ -716,7 +716,7 @@ mov ecx, 0x3412a55a
 mov dword [rax], 0x3412a55a
 mov rcx, dword -0x7bed5aa6
 mov qword [rax], qword -0x7bed5aa6
-o16 xbegin 0x7fffffffffffa54f
+xbegin 0x7fffffffffffa54f
 xbegin 0x800000003412a550
 xbegin 0x800000003412a551
 o16 enter -0x5aa6, -0x5a

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt
@@ -716,7 +716,7 @@ mov ecx,0x3412a55a
 mov dword [rax],0x3412a55a
 mov rcx,dword 0xffffffff8412a55a
 mov qword [rax],qword 0xffffffff8412a55a
-o16 xbegin 0x7fffffffffffa54f
+xbegin 0x7fffffffffffa54f
 xbegin 0x800000003412a550
 xbegin 0x800000003412a551
 o16 enter 0xa55a,0xa6

diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt
@@ -716,7 +716,7 @@ mov ecx, 0x3412a55a
 mov dword [rax], 0x3412a55a
 mov rcx, dword -0x7bed5aa6
 mov qword [rax], qword -0x7bed5aa6
-o16 xbegin 0x7fffffffffffa54f
+xbegin 0x7fffffffffffa54f
 xbegin 0x800000003412a550
 xbegin 0x800000003412a551
 o16 enter -0x5aa6, -0x5a

diff --git a/src/csharp/Intel/Generator/Enums/Formatter/Gas/CtorKind.cs b/src/csharp/Intel/Generator/Enums/Formatter/Gas/CtorKind.cs
@@ -73,6 +73,5 @@ enum CtorKind {
 		STi_ST2,
 		STIG_1a,
 		STIG_1b,
-		xbegin,
 	}
 }
diff --git a/src/csharp/Intel/Generator/Enums/Formatter/Intel/CtorKind.cs b/src/csharp/Intel/Generator/Enums/Formatter/Intel/CtorKind.cs
@@ -67,7 +67,6 @@ enum CtorKind {
 		ST1_3,
 		ST2,
 		STi_ST,
-		xbegin,
 		YA,
 		invlpga,
 	}

diff --git a/src/csharp/Intel/Generator/Enums/Formatter/Nasm/CtorKind.cs b/src/csharp/Intel/Generator/Enums/Formatter/Nasm/CtorKind.cs
@@ -88,7 +88,6 @@ enum CtorKind {
 		STIG1_2,
 		STIG2_2a,
 		STIG2_2b,
-		xbegin,
 		XLAT,
 		XY,
 		YA,

diff --git a/src/csharp/Intel/Generator/Formatters/Gas/CtorInfosData.cs b/src/csharp/Intel/Generator/Formatters/Gas/CtorInfosData.cs
@@ -442,8 +442,8 @@ public static object[][] GetData(GenTypes genTypes) {
 				new object[] { ctorKind[nameof(CtorKind.Normal_3)], code[nameof(Code.Mov_rm16_imm16)], "mov", 'w', instrOpInfoFlags[nameof(InstrOpInfoFlags.MnemonicSuffixIfMem)] },
 				new object[] { ctorKind[nameof(CtorKind.Normal_3)], code[nameof(Code.Mov_rm32_imm32)], "mov", 'l', instrOpInfoFlags[nameof(InstrOpInfoFlags.MnemonicSuffixIfMem)] },
 				new object[] { ctorKind[nameof(CtorKind.Normal_3)], code[nameof(Code.Mov_rm64_imm32)], "mov", 'q', instrOpInfoFlags[nameof(InstrOpInfoFlags.MnemonicSuffixIfMem)] },
-				new object[] { ctorKind[nameof(CtorKind.xbegin)], code[nameof(Code.Xbegin_rel16)], "xbegin", 16 },
-				new object[] { ctorKind[nameof(CtorKind.xbegin)], code[nameof(Code.Xbegin_rel32)], "xbegin", 32 | 64 },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Xbegin_rel16)], "xbegin" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Xbegin_rel32)], "xbegin" },
 				new object[] { ctorKind[nameof(CtorKind.os2_4)], code[nameof(Code.Enterw_imm16_imm8)], "enter", 'w', 16, instrOpInfoFlags[nameof(InstrOpInfoFlags.KeepOperandOrder)] },
 				new object[] { ctorKind[nameof(CtorKind.os2_4)], code[nameof(Code.Enterd_imm16_imm8)], "enter", 'l', 32, instrOpInfoFlags[nameof(InstrOpInfoFlags.KeepOperandOrder)] },
 				new object[] { ctorKind[nameof(CtorKind.os2_4)], code[nameof(Code.Enterq_imm16_imm8)], "enter", 'q', 64, instrOpInfoFlags[nameof(InstrOpInfoFlags.KeepOperandOrder)] },

diff --git a/src/csharp/Intel/Generator/Formatters/Intel/CtorInfosData.cs b/src/csharp/Intel/Generator/Formatters/Intel/CtorInfosData.cs
@@ -442,8 +442,8 @@ public static object[][] GetData(GenTypes genTypes) {
 				new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.Mov_rm16_imm16)], "mov", new OrEnumValue(instrOpInfoFlags, nameof(InstrOpInfoFlags.ShowNoMemSize_ForceSize), nameof(InstrOpInfoFlags.ShowMinMemSize_ForceSize)) },
 				new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.Mov_rm32_imm32)], "mov", new OrEnumValue(instrOpInfoFlags, nameof(InstrOpInfoFlags.ShowNoMemSize_ForceSize), nameof(InstrOpInfoFlags.ShowMinMemSize_ForceSize)) },
 				new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.Mov_rm64_imm32)], "mov", new OrEnumValue(instrOpInfoFlags, nameof(InstrOpInfoFlags.ShowNoMemSize_ForceSize), nameof(InstrOpInfoFlags.ShowMinMemSize_ForceSize)) },
-				new object[] { ctorKind[nameof(CtorKind.xbegin)], code[nameof(Code.Xbegin_rel16)], "xbegin", 16 },
-				new object[] { ctorKind[nameof(CtorKind.xbegin)], code[nameof(Code.Xbegin_rel32)], "xbegin", 32 | 64 },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Xbegin_rel16)], "xbegin" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Xbegin_rel32)], "xbegin" },
 				new object[] { ctorKind[nameof(CtorKind.os2)], code[nameof(Code.Enterw_imm16_imm8)], "enter", 16 },
 				new object[] { ctorKind[nameof(CtorKind.os2)], code[nameof(Code.Enterd_imm16_imm8)], "enter", 32 },
 				new object[] { ctorKind[nameof(CtorKind.os2)], code[nameof(Code.Enterq_imm16_imm8)], "enter", 64 },

diff --git a/src/csharp/Intel/Generator/Formatters/Nasm/CtorInfosData.cs b/src/csharp/Intel/Generator/Formatters/Nasm/CtorInfosData.cs
@@ -444,8 +444,8 @@ public static object[][] GetData(GenTypes genTypes) {
 				new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.Mov_rm16_imm16)], "mov", new OrEnumValue(instrOpInfoFlags, nameof(InstrOpInfoFlags.ShowNoMemSize_ForceSize), nameof(InstrOpInfoFlags.ShowMinMemSize_ForceSize)) },
 				new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.Mov_rm32_imm32)], "mov", new OrEnumValue(instrOpInfoFlags, nameof(InstrOpInfoFlags.ShowNoMemSize_ForceSize), nameof(InstrOpInfoFlags.ShowMinMemSize_ForceSize)) },
 				new object[] { ctorKind[nameof(CtorKind.SEX2_4)], code[nameof(Code.Mov_rm64_imm32)], "mov", signExtendInfo[nameof(SignExtendInfo.Sex4)], signExtendInfo[nameof(SignExtendInfo.Sex4to8)], new OrEnumValue(instrOpInfoFlags, nameof(InstrOpInfoFlags.ShowNoMemSize_ForceSize), nameof(InstrOpInfoFlags.ShowMinMemSize_ForceSize)) },
-				new object[] { ctorKind[nameof(CtorKind.xbegin)], code[nameof(Code.Xbegin_rel16)], "xbegin", 16 },
-				new object[] { ctorKind[nameof(CtorKind.xbegin)], code[nameof(Code.Xbegin_rel32)], "xbegin", 32 | 64 },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Xbegin_rel16)], "xbegin" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Xbegin_rel32)], "xbegin" },
 				new object[] { ctorKind[nameof(CtorKind.os_2)], code[nameof(Code.Enterw_imm16_imm8)], "enter", 16 },
 				new object[] { ctorKind[nameof(CtorKind.os_2)], code[nameof(Code.Enterd_imm16_imm8)], "enter", 32 },
 				new object[] { ctorKind[nameof(CtorKind.os_2)], code[nameof(Code.Enterq_imm16_imm8)], "enter", 64 },

diff --git a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/CtorKind.g.cs b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/CtorKind.g.cs
@@ -77,7 +77,6 @@ enum CtorKind {
 		STi_ST2,
 		STIG_1a,
 		STIG_1b,
-		xbegin,
 	}
 }
 #endif
diff --git a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfo.cs b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfo.cs
@@ -975,35 +975,6 @@ public override void GetOpInfo(FormatterOptions options, in Instruction instruct
 		}
 	}
 
-	sealed class SimpleInstrInfo_xbegin : InstrInfo {
-		readonly int bitnessFlags;
-		readonly FormatterString mnemonic;
-
-		public SimpleInstrInfo_xbegin(int bitnessFlags, string mnemonic) {
-			this.bitnessFlags = bitnessFlags;
-			this.mnemonic = new FormatterString(mnemonic);
-		}
-
-		public override void GetOpInfo(FormatterOptions options, in Instruction instruction, out InstrOpInfo info) {
-			var flags = InstrOpInfoFlags.None;
-			int instrBitness = GetBitness(instruction.CodeSize);
-			if (instrBitness == 0) {
-				// Nothing
-			}
-			else if (instrBitness == 64) {
-				if ((bitnessFlags & 16) != 0)
-					flags |= InstrOpInfoFlags.OpSize16;
-			}
-			else if ((instrBitness & bitnessFlags) == 0) {
-				if ((bitnessFlags & 16) != 0)
-					flags |= InstrOpInfoFlags.OpSize16;
-				else if ((bitnessFlags & 32) != 0)
-					flags |= InstrOpInfoFlags.OpSize32;
-			}
-			info = new InstrOpInfo(mnemonic, instruction, flags);
-		}
-	}
-
 	sealed class SimpleInstrInfo_movabs : InstrInfo {
 		readonly int memOpNumber;
 		readonly FormatterString mnemonic;

diff --git a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.cs b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.cs
@@ -363,11 +363,6 @@ static InstrInfo[] ReadInfos() {
 					instrInfo = new SimpleInstrInfo_STIG1(s, v != 0);
 					break;
 
-				case CtorKind.xbegin:
-					v = reader.ReadCompressedUInt32();
-					instrInfo = new SimpleInstrInfo_xbegin((int)v, s);
-					break;
-
 				default:
 					throw new InvalidOperationException();
 				}

diff --git a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.g.cs b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.g.cs
@@ -2296,14 +2296,11 @@ static byte[] GetSerializedInstrInfos() =>
 				0x01,// 0x1 = MnemonicSuffixIfMem
 
 				// Xbegin_rel16
-				0x31,// xbegin
+				0x01,// Normal_1
 				0xE5, 0x01,// 229 = "xbegin"
-				0x10,// 0x10
 
 				// Xbegin_rel32
-				0x31,// xbegin
-				0xE5, 0x01,// 229 = "xbegin"
-				0x60,// 0x60
+				0x00,// Previous
 
 				// Enterw_imm16_imm8
 				0x24,// os2_4

diff --git a/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/CtorKind.g.cs b/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/CtorKind.g.cs
@@ -71,7 +71,6 @@ enum CtorKind {
 		ST1_3,
 		ST2,
 		STi_ST,
-		xbegin,
 		YA,
 		invlpga,
 	}

diff --git a/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfo.cs b/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfo.cs
@@ -712,41 +712,11 @@ public override void GetOpInfo(FormatterOptions options, in Instruction instruct
 		}
 	}
 
-	sealed class SimpleInstrInfo_xbegin : InstrInfo {
-		readonly int bitnessFlags;
-		readonly FormatterString mnemonic;
-
-		public SimpleInstrInfo_xbegin(int bitnessFlags, string mnemonic) {
-			this.bitnessFlags = bitnessFlags;
-			this.mnemonic = new FormatterString(mnemonic);
-		}
-
-		public override void GetOpInfo(FormatterOptions options, in Instruction instruction, out InstrOpInfo info) {
-			var flags = InstrOpInfoFlags.None;
-			int instrBitness = GetBitness(instruction.CodeSize);
-			if (instrBitness == 0) {
-				// Nothing
-			}
-			else if (instrBitness == 64) {
-				if ((bitnessFlags & 16) != 0)
-					flags |= InstrOpInfoFlags.OpSize16;
-			}
-			else if ((instrBitness & bitnessFlags) == 0) {
-				if ((bitnessFlags & 16) != 0)
-					flags |= InstrOpInfoFlags.OpSize16;
-				else if ((bitnessFlags & 32) != 0)
-					flags |= InstrOpInfoFlags.OpSize32;
-			}
-			info = new InstrOpInfo(mnemonic, instruction, flags);
-		}
-	}
-
 	sealed class SimpleInstrInfo_k1 : InstrInfo {
 		readonly FormatterString mnemonic;
 
-		public SimpleInstrInfo_k1(string mnemonic) {
+		public SimpleInstrInfo_k1(string mnemonic) =>
 			this.mnemonic = new FormatterString(mnemonic);
-		}
 
 		public override void GetOpInfo(FormatterOptions options, in Instruction instruction, out InstrOpInfo info) {
 			info = new InstrOpInfo(mnemonic, instruction, InstrOpInfoFlags.None);

diff --git a/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.cs b/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.cs
@@ -287,11 +287,6 @@ static InstrInfo[] ReadInfos() {
 					instrInfo = new SimpleInstrInfo_STi_ST(s);
 					break;
 
-				case CtorKind.xbegin:
-					v = reader.ReadCompressedUInt32();
-					instrInfo = new SimpleInstrInfo_xbegin((int)v, s);
-					break;
-
 				case CtorKind.YA:
 					instrInfo = new SimpleInstrInfo_YA(s);
 					break;
-Original file line number
+Diff line change
@@ Expand Up / @@ -67,7 +67,6 @@ enum CtorKind { @@
     		ST1_3,
     		ST2,
     		STi_ST,
-    		xbegin,
     		YA,
     		invlpga,
     	}
@@ Expand Down @@