feat(datasheet): add analog pins to Project class

htfab · May 6, 2024 · cbb1dcb · cbb1dcb
1 parent a2c7055
commit cbb1dcb
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Showing 3 changed files with 4 additions and 3 deletions.
diff --git a/project.py b/project.py
@@ -63,6 +63,7 @@ class Args:
 class Project:
     top_verilog_filename: str
     mux_address: int
+    analog_pins: tuple[int, ...]
     commit_id: str
     sort_id: int
 

diff --git a/shuttle.py b/shuttle.py
@@ -113,8 +113,9 @@ def configure_mux(self):
                     range(len(module["analog"]))
                 ), f"analog pins are not contiguous for {module_name}"
 
+                project.analog_pins = tuple(module["analog"].values())
                 if len(module["analog"]) > 0:
-                    project_info["analog_pins"] = list(module["analog"].values())
+                    project_info["analog_pins"] = project.analog_pins
 
                 project_index.append(project_info)
                 mux_index_reverse[module_name] = mux_address
@@ -123,7 +124,6 @@ def configure_mux(self):
             if project.info.top_module not in mux_index_reverse:
                 logging.error(f"no placement found for {project}!")
                 exit(1)
-            project.mux_address = mux_index_reverse[project.info.top_module]
 
         repo = git.Repo(".")
 

diff --git a/shuttle_index.py b/shuttle_index.py
@@ -9,7 +9,7 @@ class ShuttleIndexProject(TypedDict):
     tiles: str
     repo: str
     commit: str
-    analog_pins: NotRequired[List[int]]
+    analog_pins: NotRequired[tuple[int, ...]]
 
 
 class ShuttleIndexLayout(TypedDict):