fix(CMSIS): Fix AFE_ADC_n_CTRL.ref_sel enum fields and remove depre…

…cated registers (analogdevicesinc#1069)

Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_one_regs.h

@@ -7,9 +7,7 @@
 
 /******************************************************************************
  *
- * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
- * Analog Devices, Inc.),
- * Copyright (C) 2023-2024 Analog Devices, Inc.
+ * Copyright (C) 2024 Analog Devices, Inc.
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -352,20 +350,20 @@ extern "C" {
  */
 #define MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS             0 /**< CTRL_REF_SEL Position */
 #define MXC_F_AFE_ADC_ONE_CTRL_REF_SEL                 ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS)) /**< CTRL_REF_SEL Mask */
-#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */
-#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */
+#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AIN1N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Value */
+#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AIN1N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AIN1N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Setting */
 #define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_REF1N ((uint8_t)0x1UL) /**< CTRL_REF_SEL_REF1P_AND_REF1N Value */
 #define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_REF1N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_REF1N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_REF1N Setting */
-#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_REF2N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF2P_AND_REF2N Value */
-#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_REF2N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_REF2N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_REF2N Setting */
+#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */
+#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */
 #define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AVDD_AND_AGND   ((uint8_t)0x3UL) /**< CTRL_REF_SEL_AVDD_AND_AGND Value */
 #define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_AVDD_AND_AGND   (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AVDD_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AVDD_AND_AGND Setting */
-#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND  ((uint8_t)0x4UL) /**< CTRL_REF_SEL_REF0P_AND_AGND Value */
-#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND  (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_AGND Setting */
+#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AGND  ((uint8_t)0x4UL) /**< CTRL_REF_SEL_AIN0P_AND_AGND Value */
+#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AGND  (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_AGND Setting */
 #define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_AGND  ((uint8_t)0x5UL) /**< CTRL_REF_SEL_REF1P_AND_AGND Value */
 #define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_AGND  (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_AGND Setting */
-#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_AGND  ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF2P_AND_AGND Value */
-#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_AGND  (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_AGND Setting */
+#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND  ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF0P_AND_AGND Value */
+#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND  (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_AGND Setting */
 
 #define MXC_F_AFE_ADC_ONE_CTRL_REFBUFN_EN_POS          3 /**< CTRL_REFBUFN_EN Position */
 #define MXC_F_AFE_ADC_ONE_CTRL_REFBUFN_EN              ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_CTRL_REFBUFN_EN_POS)) /**< CTRL_REFBUFN_EN Mask */
@@ -563,7 +561,10 @@ extern "C" {
  * @{
  */
 #define MXC_F_AFE_ADC_ONE_PART_ID_REV_ID_POS           0 /**< PART_ID_REV_ID Position */
-#define MXC_F_AFE_ADC_ONE_PART_ID_REV_ID               ((uint32_t)(0x7UL << MXC_F_AFE_ADC_ONE_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */
+#define MXC_F_AFE_ADC_ONE_PART_ID_REV_ID               ((uint32_t)(0x1FUL << MXC_F_AFE_ADC_ONE_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */
+
+#define MXC_F_AFE_ADC_ONE_PART_ID_ADC_SEL_POS          5 /**< PART_ID_ADC_SEL Position */
+#define MXC_F_AFE_ADC_ONE_PART_ID_ADC_SEL              ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_PART_ID_ADC_SEL_POS)) /**< PART_ID_ADC_SEL Mask */
 
 /**@} end of group AFE_ADC_ONE_PART_ID_Register */
 

Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h

@@ -7,9 +7,7 @@
 
 /******************************************************************************
  *
- * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
- * Analog Devices, Inc.),
- * Copyright (C) 2023-2024 Analog Devices, Inc.
+ * Copyright (C) 2024 Analog Devices, Inc.
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -93,7 +91,6 @@ extern "C" {
 #define MXC_R_AFE_ADC_ZERO_PGA             ((uint32_t)0x000E0001UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0xE0001</tt> */
 #define MXC_R_AFE_ADC_ZERO_WAIT_EXT        ((uint32_t)0x000F0001UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0xF0001</tt> */
 #define MXC_R_AFE_ADC_ZERO_WAIT_START      ((uint32_t)0x00100001UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x100001</tt> */
-#define MXC_R_AFE_ADC_ZERO_PART_ID         ((uint32_t)0x00110003UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x110003</tt> */
 #define MXC_R_AFE_ADC_ZERO_SYSC_SEL        ((uint32_t)0x00120003UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x120003</tt> */
 #define MXC_R_AFE_ADC_ZERO_SYS_OFF_A       ((uint32_t)0x00130003UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x130003</tt> */
 #define MXC_R_AFE_ADC_ZERO_SYS_OFF_B       ((uint32_t)0x00140003UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x140003</tt> */
@@ -194,6 +191,7 @@ extern "C" {
 #define MXC_R_AFE_ADC_ZERO_ANA_TRIM        ((uint32_t)0x00790002UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x790002</tt> */
 #define MXC_R_AFE_ADC_ZERO_SYS_CTRL        ((uint32_t)0x007A0001UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x7A0001</tt> */
 #define MXC_R_AFE_ADC_ZERO_TS_CTRL         ((uint32_t)0x007C0001UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x7C0001</tt> */
+#define MXC_R_AFE_ADC_ZERO_PART_ID         ((uint32_t)0x00910003UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x910003</tt> */
 /**@} end of group afe_adc_zero_registers */
 
 /**
@@ -352,20 +350,20 @@ extern "C" {
  */
 #define MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS            0 /**< CTRL_REF_SEL Position */
 #define MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL                ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS)) /**< CTRL_REF_SEL Mask */
-#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */
-#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */
+#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AIN1N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Value */
+#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AIN1N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AIN1N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Setting */
 #define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_REF1N ((uint8_t)0x1UL) /**< CTRL_REF_SEL_REF1P_AND_REF1N Value */
 #define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_REF1N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_REF1N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_REF1N Setting */
-#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_REF2N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF2P_AND_REF2N Value */
-#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_REF2N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_REF2N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_REF2N Setting */
+#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */
+#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */
 #define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AVDD_AND_AGND  ((uint8_t)0x3UL) /**< CTRL_REF_SEL_AVDD_AND_AGND Value */
 #define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_AVDD_AND_AGND  (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AVDD_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AVDD_AND_AGND Setting */
-#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND ((uint8_t)0x4UL) /**< CTRL_REF_SEL_REF0P_AND_AGND Value */
-#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_AGND Setting */
+#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AGND ((uint8_t)0x4UL) /**< CTRL_REF_SEL_AIN0P_AND_AGND Value */
+#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_AGND Setting */
 #define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_AGND ((uint8_t)0x5UL) /**< CTRL_REF_SEL_REF1P_AND_AGND Value */
 #define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_AGND Setting */
-#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_AGND ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF2P_AND_AGND Value */
-#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_AGND Setting */
+#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF0P_AND_AGND Value */
+#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_AGND Setting */
 
 #define MXC_F_AFE_ADC_ZERO_CTRL_REFBUFN_EN_POS         3 /**< CTRL_REFBUFN_EN Position */
 #define MXC_F_AFE_ADC_ZERO_CTRL_REFBUFN_EN             ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ZERO_CTRL_REFBUFN_EN_POS)) /**< CTRL_REFBUFN_EN Mask */
@@ -556,17 +554,6 @@ extern "C" {
 
 /**@} end of group AFE_ADC_ZERO_WAIT_EXT_Register */
 
-/**
- * @ingroup  afe_adc_zero_registers
- * @defgroup AFE_ADC_ZERO_PART_ID AFE_ADC_ZERO_PART_ID
- * @brief    Silicon Revision ID
- * @{
- */
-#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS          0 /**< PART_ID_REV_ID Position */
-#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID              ((uint32_t)(0x3FUL << MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */
-
-/**@} end of group AFE_ADC_ZERO_PART_ID_Register */
-
 /**
  * @ingroup  afe_adc_zero_registers
  * @defgroup AFE_ADC_ZERO_SYSC_SEL AFE_ADC_ZERO_SYSC_SEL
@@ -2041,6 +2028,20 @@ extern "C" {
 
 /**@} end of group AFE_ADC_ZERO_TS_CTRL_Register */
 
+/**
+ * @ingroup  afe_adc_zero_registers
+ * @defgroup AFE_ADC_ZERO_PART_ID AFE_ADC_ZERO_PART_ID
+ * @brief    Silicon Revision ID
+ * @{
+ */
+#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS          0 /**< PART_ID_REV_ID Position */
+#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID              ((uint32_t)(0x1FUL << MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */
+
+#define MXC_F_AFE_ADC_ZERO_PART_ID_ADC_SEL_POS         5 /**< PART_ID_ADC_SEL Position */
+#define MXC_F_AFE_ADC_ZERO_PART_ID_ADC_SEL             ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_PART_ID_ADC_SEL_POS)) /**< PART_ID_ADC_SEL Mask */
+
+/**@} end of group AFE_ADC_ZERO_PART_ID_Register */
+
 #ifdef __cplusplus
 }
 #endif

Libraries/CMSIS/Device/Maxim/MAX32675/Include/crc_regs.h

@@ -77,8 +77,8 @@ typedef struct {
     __IO uint32_t ctrl;                 /**< <tt>\b 0x0000:</tt> CRC CTRL Register */
     union {
         __IO uint32_t datain32;         /**< <tt>\b 0x0004:</tt> CRC DATAIN32 Register */
-        __IO uint16_t datain16[2];      /**< <tt>\b 0x0004:</tt> CRC DATAIN16 Register */
-        __IO uint8_t  datain8[4];       /**< <tt>\b 0x0004:</tt> CRC DATAIN8 Register */
+        __IO uint16_t datain16;         /**< <tt>\b 0x0004:</tt> CRC DATAIN16 Register */
+        __IO uint8_t  datain8;          /**< <tt>\b 0x0004:</tt> CRC DATAIN8 Register */
     };
     __IO uint32_t poly;                 /**< <tt>\b 0x0008:</tt> CRC POLY Register */
     __IO uint32_t val;                  /**< <tt>\b 0x000C:</tt> CRC VAL Register */

Libraries/CMSIS/Device/Maxim/MAX32675/Include/dma_regs.h

@@ -88,7 +88,7 @@ typedef struct {
     __IO uint32_t inten;                /**< <tt>\b 0x000:</tt> DMA INTEN Register */
     __I  uint32_t intfl;                /**< <tt>\b 0x004:</tt> DMA INTFL Register */
     __R  uint32_t rsv_0x8_0xff[62];
-    __IO mxc_dma_ch_regs_t    ch[8];    /**< <tt>\b 0x100:</tt> DMA CH Register */
+    __IO mxc_dma_ch_regs_t ch[8];       /**< <tt>\b 0x100:</tt> DMA CH Register */
 } mxc_dma_regs_t;
 
 /* Register offsets for module DMA */

Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.svd

@@ -361,9 +361,7 @@
      </fields>
     </register>
     <register>
-     <dim>2</dim>
-     <dimIncrement>2</dimIncrement>
-     <name>DATAIN16[%s]</name>
+     <name>DATAIN16</name>
      <description>CRC Data Input</description>
      <addressOffset>0x0004</addressOffset>
      <size>16</size>
@@ -379,9 +377,7 @@
      </fields>
     </register>
     <register>
-     <dim>4</dim>
-     <dimIncrement>1</dimIncrement>
-     <name>DATAIN8[%s]</name>
+     <name>DATAIN8</name>
      <description>CRC Data Input</description>
      <addressOffset>0x0004</addressOffset>
      <size>8</size>