Update scalafmt-core to 2.7.5

.scalafmt.conf

@@ -1,4 +1,4 @@
-version = 2.6.4
+version = 2.7.5
 
 maxColumn = 120
 align = most

src/main/scala/dotvisualizer/FirrtlDiagrammer.scala

@@ -6,8 +6,7 @@ import dotvisualizer.stage.DiagrammerStage
 import firrtl.FileUtils.isCommandAvailable
 import firrtl._
 
-/**
-  * This library implements a graphviz dot file render.
+/** This library implements a graphviz dot file render.
   */
 object FirrtlDiagrammer {
   def main(args: Array[String]): Unit = {

src/main/scala/dotvisualizer/ToLoFirrtl.scala

@@ -11,8 +11,7 @@ import firrtl.options.{Dependency, Phase}
 import firrtl.stage.{FirrtlCircuitAnnotation, Forms}
 import firrtl.transforms.BlackBoxSourceHelper
 
-/**
-  * Use these lowering transforms to prepare circuit for compiling
+/** Use these lowering transforms to prepare circuit for compiling
   */
 class ToLoFirrtl extends Phase {
   private val targets = Forms.LowFormOptimized ++ Seq(
@@ -34,8 +33,8 @@ class ToLoFirrtl extends Phase {
     annotationSeq.flatMap {
       case FirrtlCircuitAnnotation(circuit) =>
         val state = CircuitState(circuit, annotationSeq)
-        val newState = transforms.foldLeft(state) {
-          case (prevState, transform) => transform.runTransform(prevState)
+        val newState = transforms.foldLeft(state) { case (prevState, transform) =>
+          transform.runTransform(prevState)
         }
         Some(FirrtlCircuitAnnotation(newState.circuit))
       case other =>
@@ -44,8 +43,7 @@ class ToLoFirrtl extends Phase {
   }
 }
 
-/**
-  *  Workaround for https://github.com/freechipsproject/firrtl/issues/498 from @jackkoenig
+/**  Workaround for https://github.com/freechipsproject/firrtl/issues/498 from @jackkoenig
   */
 class FixupOps extends Transform with DependencyAPIMigration {
   override def prerequisites = Seq.empty

src/main/scala/dotvisualizer/dotnodes/ModuleNode.scala

@@ -46,15 +46,14 @@ case class ModuleNode(
 
       val connectionTargetNames = connections.values.map(_.split(":").head).toSet
 
-      connections.foreach {
-        case (rhs, lhs) =>
-          val source = lhs.split(":").head
-          val target = rhs.split(":").head
-
-          if (target.nonEmpty && connectionTargetNames.contains(target)) {
-            linkedHashMap(source) += target
-            linkedHashMap(target)
-          }
+      connections.foreach { case (rhs, lhs) =>
+        val source = lhs.split(":").head
+        val target = rhs.split(":").head
+
+        if (target.nonEmpty && connectionTargetNames.contains(target)) {
+          linkedHashMap(source) += target
+          linkedHashMap(target)
+        }
       }
       DiGraph(linkedHashMap)
     }
@@ -92,8 +91,7 @@ case class ModuleNode(
     rankInfo + "\n  " + s"""{ rank=same; ${outputPorts.mkString(" ")} };"""
   }
 
-  /**
-    * Renders this node
+  /** Renders this node
     * @return
     */
   def render: String = {

src/main/scala/dotvisualizer/stage/phase/GenerateDotFilePhase.scala

@@ -27,8 +27,7 @@ class GenerateDotFilePhase extends Phase {
 
   override def invalidates(a: Phase) = false
 
-  /**
-    * Make a simple css file that controls highlighting
+  /** Make a simple css file that controls highlighting
     *
     * @param targetDir where to put the css
     */
@@ -48,8 +47,7 @@ class GenerateDotFilePhase extends Phase {
     printWriter.close()
   }
 
-  /**
-    * Open an svg file using the open program
+  /** Open an svg file using the open program
     *
     * @param fileName    file to be opened
     * @param openProgram program to use
@@ -72,12 +70,12 @@ class GenerateDotFilePhase extends Phase {
 
     addCss(targetDir)
 
-    val dotProgram = annotationSeq.collectFirst {
-      case SetRenderProgramAnnotation(program) => program
+    val dotProgram = annotationSeq.collectFirst { case SetRenderProgramAnnotation(program) =>
+      program
     }.getOrElse("dot")
 
-    val dotTimeOut = annotationSeq.collectFirst {
-      case DotTimeoutSecondsAnnotation(secs) => secs
+    val dotTimeOut = annotationSeq.collectFirst { case DotTimeoutSecondsAnnotation(secs) =>
+      secs
     }.getOrElse(7)
 
     val renderer = new RenderSvg(dotProgram, dotTimeOut)
@@ -91,8 +89,8 @@ class GenerateDotFilePhase extends Phase {
     }
 
     val fileName = s"$targetDir/${circuitState.circuit.main}_hierarchy.dot"
-    val openProgram = annotationSeq.collectFirst {
-      case OpenCommandAnnotation(program) => program
+    val openProgram = annotationSeq.collectFirst { case OpenCommandAnnotation(program) =>
+      program
     }.getOrElse("open")
 
     show(fileName, openProgram)

src/main/scala/dotvisualizer/stage/phase/GetFirrtlCircuitPhase.scala

@@ -19,8 +19,8 @@ class GetFirrtlCircuitPhase extends Phase {
     val rawFirrtl = firrtl.Parser.parse(firrtlText)
     val processedFirrtlCircuit = (new ToLoFirrtl)
       .transform(Seq(FirrtlCircuitAnnotation(rawFirrtl)))
-      .collectFirst {
-        case circuitAnnotation: FirrtlCircuitAnnotation => circuitAnnotation
+      .collectFirst { case circuitAnnotation: FirrtlCircuitAnnotation =>
+        circuitAnnotation
       }
       .getOrElse {
         throw new DiagrammerException("Error: Could not lower firrtl circuit")

src/main/scala/dotvisualizer/transforms/MakeDiagramGroup.scala

@@ -18,8 +18,7 @@ class MakeDiagramGroup(renderSvg: RenderSvg) extends Transform with DependencyAP
 
   override def invalidates(a: Transform) = false
 
-  /**
-    * Creates a series of diagrams starting with the startModule and continuing
+  /** Creates a series of diagrams starting with the startModule and continuing
     * through all descendant sub-modules.
     * @param state the state to be diagrammed
     * @return
@@ -31,8 +30,8 @@ class MakeDiagramGroup(renderSvg: RenderSvg) extends Transform with DependencyAP
       s"test_run_dir/${state.circuit.main}/"
     }
 
-    val startModule = state.annotations.collectFirst {
-      case StartModuleNameAnnotation(moduleName) => moduleName
+    val startModule = state.annotations.collectFirst { case StartModuleNameAnnotation(moduleName) =>
+      moduleName
     }.getOrElse(state.circuit.main)
 
     val queue = new mutable.Queue[String]()

src/main/scala/dotvisualizer/transforms/MakeOneDiagram.scala

@@ -14,8 +14,7 @@ import firrtl.{CircuitState, DependencyAPIMigration, Transform, WDefInstance, WR
 
 import scala.collection.mutable
 
-/**
-  * Annotations specify where to start rendering.  Currently the first encountered module that matches an annotation
+/** Annotations specify where to start rendering.  Currently the first encountered module that matches an annotation
   * will start the rendering, rendering continues per the depth specified in the annotation.
   * This pass is intermixed with other low to low transforms, it is not treated as a separate
   * emit, so if so annotated it will run with every firrtl compilation.
@@ -37,8 +36,8 @@ class MakeOneDiagram(renderSvg: RenderSvg) extends Transform with DependencyAPIM
     val c = state.circuit
     val targetDir = state.annotations.collectFirst { case TargetDirAnnotation(dir) => dir }.get
 
-    val startModuleName = state.annotations.collectFirst {
-      case StartModuleNameAnnotation(moduleName) => moduleName
+    val startModuleName = state.annotations.collectFirst { case StartModuleNameAnnotation(moduleName) =>
+      moduleName
     }.getOrElse(state.circuit.main)
 
     var linesPrintedSinceFlush = 0
@@ -64,8 +63,7 @@ class MakeOneDiagram(renderSvg: RenderSvg) extends Transform with DependencyAPIM
       }
     }
 
-    /**
-      * finds the specified module name in the circuit
+    /** finds the specified module name in the circuit
       *
       * @param moduleName name to find
       * @param circuit circuit being analyzed
@@ -82,8 +80,7 @@ class MakeOneDiagram(renderSvg: RenderSvg) extends Transform with DependencyAPIM
       }
     }
 
-    /**
-      * If rendering started, construct a graph inside moduleNode
+    /** If rendering started, construct a graph inside moduleNode
       * @param modulePrefix the path to this node
       * @param myModule     the firrtl module currently being parsed
       * @param moduleNode   a node renderable to dot notation constructed from myModule
@@ -97,8 +94,7 @@ class MakeOneDiagram(renderSvg: RenderSvg) extends Transform with DependencyAPIM
       subModuleDepth: Int = 0
     ): DotNode = {
 
-      /**
-        * Half the battle here is matching references between firrtl full name for an element and
+      /** Half the battle here is matching references between firrtl full name for an element and
         * dot's reference to a connect-able module
         * Following functions compute the two kinds of name
         */

src/main/scala/dotvisualizer/transforms/ModuleLevelDiagrammer.scala

@@ -13,8 +13,7 @@ import firrtl.options.TargetDirAnnotation
 
 import scala.collection.mutable
 
-/**
-  * Represents a module instance in the graph of instances in a circuit.
+/** Represents a module instance in the graph of instances in a circuit.
   *
   * @param graphName    How `dot` will refer to this node
   * @param instanceName The instance name within the parent module
@@ -23,8 +22,7 @@ import scala.collection.mutable
 class ModuleDotNode private (val graphName: String, val instanceName: String, val moduleName: String) {
   val children = new mutable.ArrayBuffer[ModuleDotNode]()
 
-  /**
-    * Render this node as a small HTML table with the module name at the top
+  /** Render this node as a small HTML table with the module name at the top
     * and each child instance as a row
     * children are sorted by moduleName then instanceName
     * @return
@@ -59,14 +57,12 @@ class ModuleDotNode private (val graphName: String, val instanceName: String, va
   }
 }
 
-/**
-  * Is the factory for ModuleDotNode creation
+/** Is the factory for ModuleDotNode creation
   */
 object ModuleDotNode {
   var nodeCounter: Int = 0
 
-  /**
-    * This factor created a new unique dot graph node name for this instance
+  /** This factor created a new unique dot graph node name for this instance
     * @param instanceName The instance
     * @param moduleName   The module
     * @return
@@ -77,8 +73,7 @@ object ModuleDotNode {
   }
 }
 
-/**
-  * Creates a high level diagram that shows the instances in the circuit and their Module names
+/** Creates a high level diagram that shows the instances in the circuit and their Module names
   */
 //
 //TODO: Make even more links from these graph nodes back to the other generated graphs
@@ -95,8 +90,8 @@ class ModuleLevelDiagrammer(renderSvg: RenderSvg) extends Transform with Depende
   def execute(circuitState: CircuitState): CircuitState = {
     val c = circuitState.circuit
     val targetDir = circuitState.annotations.collectFirst { case TargetDirAnnotation(dir) => dir }.get
-    val startModule = circuitState.annotations.collectFirst {
-      case StartModuleNameAnnotation(moduleName) => moduleName
+    val startModule = circuitState.annotations.collectFirst { case StartModuleNameAnnotation(moduleName) =>
+      moduleName
     }.getOrElse(circuitState.circuit.main)
 
     val TopLevel = startModule + "_hierarchy"
@@ -115,8 +110,7 @@ class ModuleLevelDiagrammer(renderSvg: RenderSvg) extends Transform with Depende
 
     val top = WDefInstance(startModule, startModule)
 
-    /**
-      * Find the given instance in the Module Hierarchy
+    /** Find the given instance in the Module Hierarchy
       * This is almost certainly inefficient. Should not have to map the modules every time
       * @param instance instance being searched for
       * @return
@@ -137,8 +131,7 @@ class ModuleLevelDiagrammer(renderSvg: RenderSvg) extends Transform with Depende
       }
     }
 
-    /**
-      * Walk through the instance graph adding ModuleDotNodes and a record of their connections
+    /** Walk through the instance graph adding ModuleDotNodes and a record of their connections
       * @param wDefInstance start instance
       * @param path         underscore separated path to the start instance
       * @return

src/main/scala/dotvisualizer/transforms/RemoveTempWires.scala

@@ -30,8 +30,7 @@ class RemoveTempWires extends Transform with DependencyAPIMigration {
 
   override def invalidates(a: Transform) = false
 
-  /**
-    * Foreach Module in a firrtl circuit
+  /** Foreach Module in a firrtl circuit
     *   Find all the DefNodes with temp names and render their expression
     *   Remove all the found dev nodes
     *   recursively replace their references with their associated expression
@@ -43,17 +42,15 @@ class RemoveTempWires extends Transform with DependencyAPIMigration {
 
     val c = state.circuit
 
-    /**
-      * removes all references to temp wires in module
+    /** removes all references to temp wires in module
       * @param module the module to be altered
       * @return
       */
     def removeTempWiresFromModule(module: Module): Module = {
 
       val toRemove = new mutable.HashMap[String, Expression]()
 
-      /**
-        * Saves reference to the expression associated
+      /** Saves reference to the expression associated
         * with a temp wire associated with a Node statement
         * @param s statement to be checked
         */
@@ -75,8 +72,7 @@ class RemoveTempWires extends Transform with DependencyAPIMigration {
         case _ => //do nothing
       }
 
-      /**
-        * recursively find any references to temp wires in the expression and replace the
+      /** recursively find any references to temp wires in the expression and replace the
         * references with the associated expression
         * @param e expression to be altered
         * @return
@@ -86,7 +82,7 @@ class RemoveTempWires extends Transform with DependencyAPIMigration {
           case wire: WRef =>
             if (
               (wire.name.startsWith(RemoveTempWires.GenPrefix) ||
-              wire.name.startsWith(RemoveTempWires.TempPrefix)) && toRemove.contains(wire.name)
+                wire.name.startsWith(RemoveTempWires.TempPrefix)) && toRemove.contains(wire.name)
             ) {
               val new_node = toRemove(wire.name)
               removeGen(new_node)
@@ -96,7 +92,7 @@ class RemoveTempWires extends Transform with DependencyAPIMigration {
           case wire: WSubField =>
             if (
               (wire.name.startsWith(RemoveTempWires.GenPrefix) ||
-              wire.name.startsWith(RemoveTempWires.TempPrefix)) && toRemove.contains(wire.name)
+                wire.name.startsWith(RemoveTempWires.TempPrefix)) && toRemove.contains(wire.name)
             ) {
               val new_node = toRemove(wire.name)
               removeGen(new_node)
@@ -109,8 +105,7 @@ class RemoveTempWires extends Transform with DependencyAPIMigration {
         }
       }
 
-      /**
-        * Removes node definition statements for temp wires
+      /** Removes node definition statements for temp wires
         * @param s statement to be altered
         * @return
         */

src/test/scala/dotvisualizer/AttachExample.scala

@@ -13,8 +13,7 @@ import org.scalatest.matchers.should.Matchers
 
 import scala.io.Source
 
-/**
-  * Checks that attaches are double headed arrows connected to each node
+/** Checks that attaches are double headed arrows connected to each node
   */
 class AttachExample extends AnyFreeSpec with Matchers {
 

src/test/scala/dotvisualizer/HierarchicalModulesExample.scala

@@ -13,8 +13,7 @@ import org.scalatest.freespec.AnyFreeSpec
 import org.scalatest.matchers.should.Matchers
 import scala.language.reflectiveCalls
 
-/**
-  * This class has parameterizable widths, it will generate different hardware
+/** This class has parameterizable widths, it will generate different hardware
   *
   * @param widthC io width
   */
@@ -27,8 +26,7 @@ class VizModC(widthC: Int) extends Module {
   io.out := io.in
 }
 
-/**
-  * instantiates a C of a particular size, VizModA does not generate different hardware
+/** instantiates a C of a particular size, VizModA does not generate different hardware
   * based on it's parameter
   * @param annoParam  parameter is only used in annotation not in circuit
   */