Add supoort for hpm6360evk

freakishness · Feb 18, 2024 · bfc9272 · bfc9272
1 parent a1af2e7
commit bfc9272
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diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig
@@ -238,6 +238,17 @@ config ARCH_CHIP_QEMU_RV
 	---help---
 		QEMU Generic RV32/RV64 processor
 
+config ARCH_CHIP_HPM6000
+	bool "Hpmicro HPM6000"
+	select ARCH_RV32
+	select ARCH_RV_ISA_M
+	select ARCH_RV_ISA_A
+	select ARCH_RV_ISA_C
+	select ONESHOT
+	select ALARM_ARCH
+	---help---
+		Hpmicro HPM6000 processor (D45 RISC-V Core with MAC extensions).
+
 config ARCH_CHIP_HPM6750
 	bool "Hpmicro HPM6750"
 	select ARCH_RV32

diff --git a/arch/risc-v/src/hpm6000/CMakeLists.txt b/arch/risc-v/src/hpm6000/CMakeLists.txt
@@ -0,0 +1,37 @@
+# ##############################################################################
+# arch/arm/src/qemu-rv/CMakeLists.txt
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+set(SRCS hpm_head.S)
+
+list(
+  APPEND
+  SRCS
+  hpm_clockconfig.c
+  hpm_gpio.c
+  hpm_ioc.c
+  hpm_irq.c
+  hpm_irq_dispatch.c
+  hpm_lowputc.c
+  hpm_serial.c
+  hpm_start.c
+  hpm_timerisr.c
+)
+
+target_sources(arch PRIVATE ${SRCS})
diff --git a/arch/risc-v/src/hpm6000/Kconfig b/arch/risc-v/src/hpm6000/Kconfig
@@ -21,7 +21,7 @@ endchoice # HPM6000 Chip Selection
 config ARCH_FAMILY_HPM6360
 	bool
 	default n
-	select ARCH_FAMILY_HPM6000
+	select ARCH_FAMILY_HPM6300
 
 # Peripheral support
 

diff --git a/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_ioc.h b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_ioc.h
@@ -626,4 +626,16 @@
 #define HPM_IOC_PAD_PZ07_FUNC_CTL          (HPM_IOC_BASE + HPM_IOC_PAD_PZ07_FUNC_CTL_OFFSET)
 #define HPM_IOC_PAD_PZ07_PAD_CTL           (HPM_IOC_BASE + HPM_IOC_PAD_PZ07_PAD_CTL_OFFSET )
 
+#define HPM_PIOC_PAD_FUNC_CTL_ADDRESS(n)   (HPM_PIOC_BASE + HPM_IOC_PAD_FUNC_CTL_OFFSET(n))
+#define HPM_PIOC_PAD_PAD_CTL_ADDRESS(n)    (HPM_PIOC_BASE + HPM_IOC_PAD_PAD_CTL_OFFSET(n))
+
+#define HPM_PIOC_PAD_PY00_FUNC_CTL         (HPM_PIOC_BASE + HPM_IOC_PAD_PY00_FUNC_CTL_OFFSET)
+#define HPM_PIOC_PAD_PY01_FUNC_CTL         (HPM_PIOC_BASE + HPM_IOC_PAD_PY01_FUNC_CTL_OFFSET)
+#define HPM_PIOC_PAD_PY02_FUNC_CTL         (HPM_PIOC_BASE + HPM_IOC_PAD_PY02_FUNC_CTL_OFFSET)
+#define HPM_PIOC_PAD_PY03_FUNC_CTL         (HPM_PIOC_BASE + HPM_IOC_PAD_PY03_FUNC_CTL_OFFSET)
+#define HPM_PIOC_PAD_PY04_FUNC_CTL         (HPM_PIOC_BASE + HPM_IOC_PAD_PY04_FUNC_CTL_OFFSET)
+#define HPM_PIOC_PAD_PY05_FUNC_CTL         (HPM_PIOC_BASE + HPM_IOC_PAD_PY05_FUNC_CTL_OFFSET)
+#define HPM_PIOC_PAD_PY06_FUNC_CTL         (HPM_PIOC_BASE + HPM_IOC_PAD_PY06_FUNC_CTL_OFFSET)
+#define HPM_PIOC_PAD_PY07_FUNC_CTL         (HPM_PIOC_BASE + HPM_IOC_PAD_PY07_FUNC_CTL_OFFSET)
+
 #endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_IOC_H */
diff --git a/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pcfg.h b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pcfg.h
@@ -0,0 +1,118 @@
+/****************************************************************************
+ * arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pcfg.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PCFG_H
+#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PCFG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "hpm_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define HPM_PCFG_BANDGAP (HPM_PCFG_BASE + 0x0000)
+#define HPM_PCFG_LDO1P1  (HPM_PCFG_BASE + 0x0004)
+#define HPM_PCFG_LDO2P5  (HPM_PCFG_BASE + 0x0008)
+#define HPM_PCFG_DCDC_MODE (HPM_PCFG_BASE + 0x0010)
+#define HPM_PCFG_DCDC_LPMODE   (HPM_PCFG_BASE + 0x0014)
+#define HPM_PCFG_DCDC_PROT  (HPM_PCFG_BASE + 0x0018)
+#define HPM_PCFG_DCDC_CURRENT  (HPM_PCFG_BASE + 0x001C)
+#define HPM_PCFG_DCDC_ADVMODE  (HPM_PCFG_BASE + 0x0020)
+#define HPM_PCFG_DCDC_ADVPARAM (HPM_PCFG_BASE + 0x0024)
+#define HPM_PCFG_DCDC_MISC (HPM_PCFG_BASE + 0x0028)
+#define HPM_PCFG_DCDC_DEBUG (HPM_PCFG_BASE + 0x002C)
+#define HPM_PCFG_DCDC_START_TIME (HPM_PCFG_BASE + 0x0030)
+#define HPM_PCFG_DCDC_RESUME_TIME (HPM_PCFG_BASE + 0x0034)
+#define HPM_PCFG_POWER_TRAP (HPM_PCFG_BASE + 0x0040)
+#define HPM_PCFG_WAKE_CAUSE (HPM_PCFG_BASE + 0x0044)
+#define HPM_PCFG_WAK_MASK (HPM_PCFG_BASE + 0x0048)
+#define HPM_PCFG_SCG_CTRL (HPM_PCFG_BASE + 0x004C)
+#define HPM_PCFG_DEBUG_STOP (HPM_PCFG_BASE + 0x0050)
+#define HPM_PCFG_RC24M (HPM_PCFG_BASE + 0x0060)
+#define HPM_PCFG_RC24M_TRACK (HPM_PCFG_BASE + 0x0064)
+#define HPM_PCFG_TRACK_TARGET (HPM_PCFG_BASE + 0x0068)
+#define HPM_PCFG_STATUS (HPM_PCFG_BASE + 0x006C)
+
+#define HPM_PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0)
+#define HPM_PCFG_BANDGAP_VBG_P50_TRIM_MASK  (0x1F << HPM_PCFG_BANDGAP_VBG_P50_TRIM_SHIFT)
+#define HPM_PCFG_BANDGAP_VBG_P50_TRIM(n)    ((n) << HPM_PCFG_BANDGAP_VBG_P50_TRIM_SHIFT)
+
+#define HPM_PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8)
+#define HPM_PCFG_BANDGAP_VBG_P65_TRIM_MASK  (0x1F << HPM_PCFG_BANDGAP_VBG_P65_TRIM_SHIFT)
+#define HPM_PCFG_BANDGAP_VBG_P65_TRIM(n)    ((n) << HPM_PCFG_BANDGAP_VBG_P65_TRIM_SHIFT)
+
+#define HPM_PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16)
+#define HPM_PCFG_BANDGAP_VBG_1P0_TRIM_MASK  (0x1F << HPM_PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT)
+#define HPM_PCFG_BANDGAP_VBG_1P0_TRIM(n)    ((n) << HPM_PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT)
+
+#define HPM_PCFG_BANDGAP_POWER_SAVE_SHIFT (24)
+#define HPM_PCFG_BANDGAP_POWER_SAVE_NORMAL  (0 << HPM_PCFG_BANDGAP_POWER_SAVE_SHIFT)
+#define HPM_PCFG_BANDGAP_POWER_SAVE_LOW     (1 << HPM_PCFG_BANDGAP_POWER_SAVE_SHIFT)
+
+#define HPM_PCFG_BANDGAP_LOWPOWER_MODE_SHIFT (25)
+#define HPM_PCFG_BANDGAP_LOWPOWER_MODE_NORMAL  (0 << HPM_PCFG_BANDGAP_LOWPOWER_MODE_SHIFT)
+#define HPM_PCFG_BANDGAP_LOWPOWER_MODE_LOW     (1 << HPM_PCFG_BANDGAP_LOWPOWER_MODE_SHIFT)
+
+#define HPM_PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31)
+#define HPM_PCFG_BANDGAP_VBG_TRIMMED_UNCALIBRATED  (0 << HPM_PCFG_BANDGAP_VBG_TRIMMED_SHIFT)
+#define HPM_PCFG_BANDGAP_VBG_TRIMMED_CALIBRATED    (1 << HPM_PCFG_BANDGAP_VBG_TRIMMED_SHIFT)
+
+#define HPM_PCFG_LDO1P1_VOLT_SHIFT (0)
+#define HPM_PCFG_LDO1P1_VOLT_MASK  (0x7FF << HPM_PCFG_LDO1P1_VOLT_SHIFT)
+#define HPM_PCFG_LDO1P1_VOLT(n)    ((n) << HPM_PCFG_LDO1P1_VOLT_SHIFT)
+
+#define HPM_PCFG_LDO2P5_VOLT_SHIFT (0)
+#define HPM_PCFG_LDO2P5_VOLT_MASK  (0x7FF << HPM_PCFG_LDO2P5_VOLT_SHIFT)
+#define HPM_PCFG_LDO2P5_VOLT(n)    ((n) << HPM_PCFG_LDO2P5_VOLT_SHIFT)
+
+#define HPM_PCFG_LDO2P5_ENABLE_SHIFT (16)
+#define HPM_PCFG_LDO2P5_ENABLE_DISABLE  (0 << HPM_PCFG_LDO2P5_ENABLE_SHIFT)
+#define HPM_PCFG_LDO2P5_ENABLE_ENABLE   (1 << HPM_PCFG_LDO2P5_ENABLE_SHIFT)
+
+#define HPM_PCFG_LDO2P5_READY_SHIFT (28)
+#define HPM_PCFG_LDO2P5_READY_NOT_READY  (0 << HPM_PCFG_LDO2P5_READY_SHIFT)
+#define HPM_PCFG_LDO2P5_READY_READY      (1 << HPM_PCFG_LDO2P5_READY_SHIFT)
+
+#define HPM_PCFG_DCDC_MODE_VOLT_SHIFT (0)
+#define HPM_PCFG_DCDC_MODE_VOLT_MASK  (0x7FF << HPM_PCFG_DCDC_MODE_VOLT_SHIFT)
+#define HPM_PCFG_DCDC_MODE_VOLT(n)    ((n) << HPM_PCFG_DCDC_MODE_VOLT_SHIFT)
+
+#define HPM_PCFG_DCDC_MODE_MODE_SHIFT (16)
+#define HPM_PCFG_DCDC_MODE_MODE_MASK  (0x07 << HPM_PCFG_DCDC_MODE_MODE_SHIFT)
+#define HPM_PCFG_DCDC_MODE_MODE(n)    ((n) << HPM_PCFG_DCDC_MODE_MODE_SHIFT)
+#define HPM_PCFG_DCDC_MODE_CLOSE  (0 << HPM_PCFG_DCDC_MODE_MODE_SHIFT)
+#define HPM_PCFG_DCDC_MODE_NORMAL (1 << HPM_PCFG_DCDC_MODE_MODE_SHIFT)
+#define HPM_PCFG_DCDC_MODE_UNIVERSAL  (3 << HPM_PCFG_DCDC_MODE_MODE_SHIFT)
+#define HPM_PCFG_DCDC_MODE_PRO  (7 << HPM_PCFG_DCDC_MODE_MODE_SHIFT)
+
+#define HPM_PCFG_DCDC_MODE_READY_SHIFT (28)
+#define HPM_PCFG_DCDC_MODE_READY_NOT_READY  (0 << HPM_PCFG_DCDC_MODE_READY_SHIFT)
+#define HPM_PCFG_DCDC_MODE_READY_READY      (1 << HPM_PCFG_DCDC_MODE_READY_SHIFT)
+
+#define HPM_PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0)
+#define HPM_PCFG_DCDC_LPMODE_STBY_VOLT_MASK  (0x7FF << HPM_PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT)
+#define HPM_PCFG_DCDC_LPMODE_STBY_VOLT(n)    ((n) << HPM_PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT)
+
+#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PCFG_H */
diff --git a/arch/risc-v/src/hpm6000/hpm.h b/arch/risc-v/src/hpm6000/hpm.h
@@ -18,8 +18,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_RISCV_SRC_HPM6750_HPM6750_H
-#define __ARCH_RISCV_SRC_HPM6750_HPM6750_H
+#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_H
+#define __ARCH_RISCV_SRC_HPM6000_HPM_H
 
 /****************************************************************************
  * Included Files
@@ -34,4 +34,4 @@
 #include "riscv_internal.h"
 #include "chip.h"
 
-#endif /* __ARCH_RISCV_SRC_HPM6000_HPM6750_H */
+#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_H */
diff --git a/arch/risc-v/src/hpm6000/hpm_clockconfig.c b/arch/risc-v/src/hpm6000/hpm_clockconfig.c
@@ -81,65 +81,72 @@ void hpm_clockconfig(void)
 
   value = getreg32(0xf40c4010);
   value &= ~0xfff;
-  value |= 1100;
+  value |= 0x1044c;
   putreg32(value, 0xf40c4010);
 
-  value = getreg32(HPM_PLLCTLV2_XTAL);
-  value &= HPM_PLLCTLV2_XTAL_RAMP_TIME_MASK;
-  value |= HPM_PLLCTLV2_XTAL_RAMP_TIME(32UL * 1000UL * 9U);
-  putreg32(value, HPM_PLLCTLV2_XTAL);
-
-  value = getreg32(HPM_SYSCTL_GLOBAL00);
-  value &= ~SYSCTL_GLOBAL00_MUX_MASK;
-  value |= SYSCTL_GLOBAL00_MUX(2);
-  putreg32(value, HPM_SYSCTL_GLOBAL00);
-
   /* uart should configure pin function before opening clock */
 
   value = 0xffffffff &
           ~(SYSCTL_GROUP0_LINK0_UART0 | SYSCTL_GROUP0_LINK0_UART1 |
             SYSCTL_GROUP0_LINK0_UART2 | SYSCTL_GROUP0_LINK0_UART3 |
             SYSCTL_GROUP0_LINK0_UART4 | SYSCTL_GROUP0_LINK0_UART5 |
             SYSCTL_GROUP0_LINK0_UART6);
-  putreg32(value, HPM_SYSCTL_GROUP0_LINK0_SET);
+  putreg32(0x01f7ffff, HPM_SYSCTL_GROUP0_LINK0_VALUE);
 
   value = 0xffffffff & ~SYSCTL_GROUP0_LINK1_UART7;
-  putreg32(value, HPM_SYSCTL_GROUP0_LINK1_SET);
+  putreg32(0x3dfffffe, HPM_SYSCTL_GROUP0_LINK1_VALUE);
 
   /* Connect Group0 to CPU0 */
 
   putreg32(1, HPM_SYSCTL_AFFILIATE_CPU0_SET);
 
+  value = getreg32(HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0);
+  if ((value & 0xff) == 1)
+    {
+      value = SYSCTL_CLOCK_CPU_MUX_PLL1_CLK0 |
+              SYSCTL_CLOCK_CPU_DIV(CPU_DIV) |
+              SYSCTL_CLOCK_CPU_SUB0_DIV(AXI_SUB_DIV - 1) |
+              SYSCTL_CLOCK_CPU_SUB1_DIV(AHB_SUB_DIV - 1);
+      putreg32(value, HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0);
+      while (getreg32(HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0) & 0x80000000);
+    }
+
   /* Configure CPU0 clock & AXI Sub-clock & AHB Sub-clock */
 
   value = SYSCTL_CLOCK_CPU_MUX_PLL1_CLK0 |
           SYSCTL_CLOCK_CPU_DIV(CPU_DIV - 1) |
           SYSCTL_CLOCK_CPU_SUB0_DIV(AXI_SUB_DIV - 1) |
           SYSCTL_CLOCK_CPU_SUB1_DIV(AHB_SUB_DIV - 1);
   putreg32(value, HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0);
+  while (getreg32(HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0) & 0x80000000);
 
 #if defined (CONFIG_ARCH_FAMILY_HPM6300)
   /* Configure PLL1_CLK0 Post Divider */
 
   value = (getreg32(HPM_PLLCTLV2_PLL1_DIV0) &
           ~HPM_PLLCTLV2_PLL_DIV_DIV_MASK) |
-          HPM_PLLCTLV2_PLL_DIV_DIV(PLL1_DIV);
+          HPM_PLLCTLV2_PLL_DIV_DIV(PLL1_DIV) |
+          HPM_PLLCTLV2_PLL_DIV_ENABLE;
   putreg32(value, HPM_PLLCTLV2_PLL1_DIV0);
+  while (getreg32(HPM_PLLCTLV2_PLL1_DIV0) & 0x80000000);
 #endif
   /* Configure PLL1 clock frequencey */
 
   value = PLL1_FREQ / PLLCTLV2_PLL_XTAL_FREQ - 1;
   putreg32(value, HPM_PLLCTLV2_PLL1_MFI);
+  while (getreg32(HPM_PLLCTLV2_PLL1_MFI) & 0x80000000);
+  putreg32(value + 1, HPM_PLLCTLV2_PLL1_MFI);
+  while (getreg32(HPM_PLLCTLV2_PLL1_MFI) & 0x80000000);
 
   value = PLL1_FREQ % PLLCTLV2_PLL_XTAL_FREQ * PLLCTLV2_PLL_MFN_FACTOR;
   putreg32(value, HPM_PLLCTLV2_PLL1_MFN);
+  while (getreg32(HPM_PLLCTLV2_PLL1_MFN) & 0x80000000);
 
-  /* Configure AUD */
-
-  value = (getreg32(HPM_SYSCTL_CLOCK_CLK_TOP_AUD1) &
-           ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) |
-          (SYSCTL_CLOCK_MUX_PLL2_CLK0 | SYSCTL_CLOCK_DIV(AUD_DIV - 1));
-  putreg32(value, HPM_SYSCTL_CLOCK_CLK_TOP_AUD1);
+  value = (getreg32(HPM_SYSCTL_CLOCK_CLK_TOP_MCT0) &
+          ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) |
+          (SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1));
+  putreg32(value, HPM_SYSCTL_CLOCK_CLK_TOP_MCT0);
+  while (getreg32(HPM_SYSCTL_CLOCK_CLK_TOP_MCT0) & 0x40000000);
 }
 
 void hpm_uart_clockconfig(void)
@@ -151,6 +158,7 @@ void hpm_uart_clockconfig(void)
 #ifdef CONFIG_HPM_UART0
   putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1),
            HPM_SYSCTL_CLOCK_CLK_TOP_UART0);
+  while (getreg32(HPM_SYSCTL_CLOCK_CLK_TOP_UART0) & 0x40000000);
   value |= SYSCTL_GROUP0_LINK0_UART0;
 #endif
 

diff --git a/arch/risc-v/src/hpm6000/hpm_gpio.c b/arch/risc-v/src/hpm6000/hpm_gpio.c
@@ -170,15 +170,19 @@ static inline int hpm_gpio_configperiph(gpio_pinset_t pinset)
   ioc_pinset_t ioset;
   uintptr_t regaddr;
 
-  index = ((pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
+  index = ((pinset & GPIO_PADMUX_MASK) >> GPIO_PADMUX_SHIFT);
   ioset = (ioc_pinset_t)(pinset & GPIO_IOCPAD_MASK) >> GPIO_IOCPAD_SHIFT;
 
-  index = hpm_iocpad_map(index);
-
   regaddr = HPM_IOC_PAD_PAD_CTL_ADDRESS(index);
 
   hpm_iocpad_configure(regaddr, ioset);
 
+  if (index >= HPM_IOC_PAD_PY00_INDEX)
+    {
+      regaddr = HPM_PIOC_PAD_PAD_CTL_ADDRESS(index);
+      hpm_iocpad_configure(regaddr, PAD_ALT3);
+    }
+
   return OK;
 }
 

diff --git a/arch/risc-v/src/hpm6000/hpm_gpio.h b/arch/risc-v/src/hpm6000/hpm_gpio.h
@@ -175,7 +175,7 @@
  */
 
 #define GPIO_PADMUX_SHIFT   (16)
-#define GPIO_PADMUX_MASK    (0xff << GPIO_PADMUX_SHIFT)
+#define GPIO_PADMUX_MASK    (0xfff << GPIO_PADMUX_SHIFT)
 #  define GPIO_PADMUX(n)    ((uint32_t)(n) << GPIO_PADMUX_SHIFT)
 #define GPIO_PADMUX_GET(n)  ((n&GPIO_PADMUX_MASK) >> GPIO_PADMUX_SHIFT)
 

diff --git a/arch/risc-v/src/hpm6000/hpm_ioc.c b/arch/risc-v/src/hpm6000/hpm_ioc.c
@@ -256,7 +256,7 @@ int hpm_iocpad_configure(uintptr_t padctl, ioc_pinset_t ioset)
 
   /* Configure analog */
 
-  if ((ioset & FUNC_ANALOG_MASK) == 0)
+  if ((ioset & FUNC_ANALOG_MASK) == FUNC_ANALOG)
     {
       regval |= IOC_PAD_FUNC_ANALOG;
       putreg32(regval, funcctl);

diff --git a/arch/risc-v/src/hpm6000/hpm_ioc.h b/arch/risc-v/src/hpm6000/hpm_ioc.h
@@ -134,7 +134,7 @@
  */
 #define FUNC_ANALOG_SHIFT     (4)
 #define FUNC_ANALOG_MASK      (7 << FUNC_ANALOG_SHIFT)
-#define FUNC_ANALOG           (0 << FUNC_ANALOG_SHIFT)
+#define FUNC_ANALOG           (1 << FUNC_ANALOG_SHIFT)
 
 /* Output Slew Rate:
  *