Add 4-byte alignment check on pc in branching instructions

[mininny]

Description

The RISC-V specifications indicate the following in section "2.5.2. Conditional Branches".

The conditional branch instructions will generate an instruction-address-misaligned exception if the
target address is not aligned to a four-byte boundary and the branch condition evaluates to true. If the
branch condition evaluates to false, the instruction-address-misaligned exception will not be raised.

However, the three implementations (fast, slow, solidity) succeed when a conditional branch instruction sets a program counter pc not aligned on 4 bytes.

The branching opcode (0x63) implementation should raise an exception when the new program counter pc is not aligned on 4 bytes.

[codecov-commenter]

Codecov Report

Attention: Patch coverage is 0% with 6 lines in your changes missing coverage. Please review.

Project coverage is 61.80%. Comparing base (8ff9318) to head (ba4ab1a).

Files with missing lines	Patch %	Lines
rvgo/fast/vm.go	0.00%	2 Missing and 1 partial ⚠️
rvgo/slow/vm.go	0.00%	2 Missing and 1 partial ⚠️

Additional details and impacted files

@@            Coverage Diff             @@
##           master     #102      +/-   ##
==========================================
- Coverage   61.89%   61.80%   -0.10%     
==========================================
  Files          27       27              
  Lines        4091     4097       +6     
==========================================
  Hits         2532     2532              
- Misses       1427     1431       +4     
- Partials      132      134       +2     

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