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Clean up a bit (#2275)
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@bugadani
bugadani authored Oct 4, 2024
1 parent a4fe5e6 commit d3f0304
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Showing 7 changed files with 296 additions and 609 deletions.
105 changes: 13 additions & 92 deletions esp-hal/src/dma/gdma.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -135,30 +135,6 @@ impl<C: GdmaChannel> RegisterAccess for ChannelTxImpl<C> {
.modify(|_, w| w.outlink_restart().set_bit());
}

fn clear_interrupts(&self) {
#[cfg(not(esp32s3))]
self.int().clr().write(|w| {
w.out_eof().clear_bit_by_one();
w.out_dscr_err().clear_bit_by_one();
w.out_done().clear_bit_by_one();
w.out_total_eof().clear_bit_by_one();
w.outfifo_ovf().clear_bit_by_one();
w.outfifo_udf().clear_bit_by_one()
});

#[cfg(esp32s3)]
self.int().clr().write(|w| {
w.out_eof().clear_bit_by_one();
w.out_dscr_err().clear_bit_by_one();
w.out_done().clear_bit_by_one();
w.out_total_eof().clear_bit_by_one();
w.outfifo_ovf_l1().clear_bit_by_one();
w.outfifo_ovf_l3().clear_bit_by_one();
w.outfifo_udf_l1().clear_bit_by_one();
w.outfifo_udf_l3().clear_bit_by_one()
});
}

#[cfg(esp32s3)]
fn set_ext_mem_block_size(&self, size: DmaExtMemBKSize) {
self.ch()
Expand All @@ -178,28 +154,14 @@ impl<C: GdmaChannel> TxRegisterAccess for ChannelTxImpl<C> {
}

impl<C: GdmaChannel> InterruptAccess<DmaTxInterrupt> for ChannelTxImpl<C> {
fn listen(&self, interrupts: impl Into<EnumSet<DmaTxInterrupt>>) {
fn enable_listen(&self, interrupts: EnumSet<DmaTxInterrupt>, enable: bool) {
self.int().ena().modify(|_, w| {
for interrupt in interrupts.into() {
match interrupt {
DmaTxInterrupt::TotalEof => w.out_total_eof().set_bit(),
DmaTxInterrupt::DescriptorError => w.out_dscr_err().set_bit(),
DmaTxInterrupt::Eof => w.out_eof().set_bit(),
DmaTxInterrupt::Done => w.out_done().set_bit(),
};
}
w
})
}

fn unlisten(&self, interrupts: impl Into<EnumSet<DmaTxInterrupt>>) {
self.int().ena().modify(|_, w| {
for interrupt in interrupts.into() {
for interrupt in interrupts {
match interrupt {
DmaTxInterrupt::TotalEof => w.out_total_eof().clear_bit(),
DmaTxInterrupt::DescriptorError => w.out_dscr_err().clear_bit(),
DmaTxInterrupt::Eof => w.out_eof().clear_bit(),
DmaTxInterrupt::Done => w.out_done().clear_bit(),
DmaTxInterrupt::TotalEof => w.out_total_eof().bit(enable),
DmaTxInterrupt::DescriptorError => w.out_dscr_err().bit(enable),
DmaTxInterrupt::Eof => w.out_eof().bit(enable),
DmaTxInterrupt::Done => w.out_done().bit(enable),
};
}
w
Expand Down Expand Up @@ -352,32 +314,6 @@ impl<C: GdmaChannel> RegisterAccess for ChannelRxImpl<C> {
.modify(|_, w| w.inlink_restart().set_bit());
}

fn clear_interrupts(&self) {
#[cfg(not(esp32s3))]
self.int().clr().write(|w| {
w.in_suc_eof().clear_bit_by_one();
w.in_err_eof().clear_bit_by_one();
w.in_dscr_err().clear_bit_by_one();
w.in_dscr_empty().clear_bit_by_one();
w.in_done().clear_bit_by_one();
w.infifo_ovf().clear_bit_by_one();
w.infifo_udf().clear_bit_by_one()
});

#[cfg(esp32s3)]
self.int().clr().write(|w| {
w.in_suc_eof().clear_bit_by_one();
w.in_err_eof().clear_bit_by_one();
w.in_dscr_err().clear_bit_by_one();
w.in_dscr_empty().clear_bit_by_one();
w.in_done().clear_bit_by_one();
w.infifo_ovf_l1().clear_bit_by_one();
w.infifo_ovf_l3().clear_bit_by_one();
w.infifo_udf_l1().clear_bit_by_one();
w.infifo_udf_l3().clear_bit_by_one()
});
}

#[cfg(esp32s3)]
fn set_ext_mem_block_size(&self, size: DmaExtMemBKSize) {
self.ch()
Expand All @@ -395,36 +331,21 @@ impl<C: GdmaChannel> RxRegisterAccess for ChannelRxImpl<C> {
}

impl<C: GdmaChannel> InterruptAccess<DmaRxInterrupt> for ChannelRxImpl<C> {
fn listen(&self, interrupts: impl Into<EnumSet<DmaRxInterrupt>>) {
fn enable_listen(&self, interrupts: EnumSet<DmaRxInterrupt>, enable: bool) {
self.int().ena().modify(|_, w| {
for interrupt in interrupts.into() {
for interrupt in interrupts {
match interrupt {
DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().set_bit(),
DmaRxInterrupt::ErrorEof => w.in_err_eof().set_bit(),
DmaRxInterrupt::DescriptorError => w.in_dscr_err().set_bit(),
DmaRxInterrupt::DescriptorEmpty => w.in_dscr_empty().set_bit(),
DmaRxInterrupt::Done => w.in_done().set_bit(),
DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().bit(enable),
DmaRxInterrupt::ErrorEof => w.in_err_eof().bit(enable),
DmaRxInterrupt::DescriptorError => w.in_dscr_err().bit(enable),
DmaRxInterrupt::DescriptorEmpty => w.in_dscr_empty().bit(enable),
DmaRxInterrupt::Done => w.in_done().bit(enable),
};
}
w
});
}

fn unlisten(&self, interrupts: impl Into<EnumSet<DmaRxInterrupt>>) {
self.int().ena().modify(|_, w| {
for interrupt in interrupts.into() {
match interrupt {
DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().clear_bit(),
DmaRxInterrupt::ErrorEof => w.in_err_eof().clear_bit(),
DmaRxInterrupt::DescriptorError => w.in_dscr_err().clear_bit(),
DmaRxInterrupt::DescriptorEmpty => w.in_dscr_empty().clear_bit(),
DmaRxInterrupt::Done => w.in_done().clear_bit(),
};
}
w
})
}

fn is_listening(&self) -> EnumSet<DmaRxInterrupt> {
let mut result = EnumSet::new();

Expand Down
29 changes: 18 additions & 11 deletions esp-hal/src/dma/mod.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1684,7 +1684,7 @@ where

compiler_fence(core::sync::atomic::Ordering::SeqCst);

self.rx_impl.clear_interrupts();
self.rx_impl.clear_all();
self.rx_impl.reset();
self.rx_impl.set_link_addr(chain.first() as u32);
self.rx_impl.set_peripheral(peri as u8);
Expand All @@ -1706,7 +1706,7 @@ where

compiler_fence(core::sync::atomic::Ordering::SeqCst);

self.rx_impl.clear_interrupts();
self.rx_impl.clear_all();
self.rx_impl.reset();
self.rx_impl.set_link_addr(preparation.start as u32);
self.rx_impl.set_peripheral(peri as u8);
Expand Down Expand Up @@ -1767,7 +1767,7 @@ where
}

fn clear_interrupts(&self) {
self.rx_impl.clear_interrupts();
self.rx_impl.clear_all();
}

fn waker(&self) -> &'static embassy_sync::waitqueue::AtomicWaker {
Expand Down Expand Up @@ -1891,7 +1891,7 @@ where

compiler_fence(core::sync::atomic::Ordering::SeqCst);

self.tx_impl.clear_interrupts();
self.tx_impl.clear_all();
self.tx_impl.reset();
self.tx_impl.set_link_addr(chain.first() as u32);
self.tx_impl.set_peripheral(peri as u8);
Expand Down Expand Up @@ -1921,7 +1921,7 @@ where

compiler_fence(core::sync::atomic::Ordering::SeqCst);

self.tx_impl.clear_interrupts();
self.tx_impl.clear_all();
self.tx_impl.reset();
self.tx_impl.set_link_addr(preparation.start as u32);
self.tx_impl.set_peripheral(peri as u8);
Expand Down Expand Up @@ -1976,7 +1976,7 @@ where
}

fn clear_interrupts(&self) {
self.tx_impl.clear_interrupts();
self.tx_impl.clear_all();
}

fn last_out_dscr_address(&self) -> usize {
Expand Down Expand Up @@ -2012,9 +2012,6 @@ pub trait RegisterAccess: crate::private::Sealed {
/// Mount a new descriptor.
fn restart(&self);

/// Clear all interrupt bits
fn clear_interrupts(&self);

#[cfg(esp32s3)]
fn set_ext_mem_block_size(&self, size: DmaExtMemBKSize);
}
Expand All @@ -2033,8 +2030,18 @@ pub trait TxRegisterAccess: RegisterAccess {

#[doc(hidden)]
pub trait InterruptAccess<T: EnumSetType>: crate::private::Sealed {
fn listen(&self, interrupts: impl Into<EnumSet<T>>);
fn unlisten(&self, interrupts: impl Into<EnumSet<T>>);
fn listen(&self, interrupts: impl Into<EnumSet<T>>) {
self.enable_listen(interrupts.into(), true)
}
fn unlisten(&self, interrupts: impl Into<EnumSet<T>>) {
self.enable_listen(interrupts.into(), false)
}

fn clear_all(&self) {
self.clear(EnumSet::all());
}

fn enable_listen(&self, interrupts: EnumSet<T>, enable: bool);
fn is_listening(&self) -> EnumSet<T>;
fn clear(&self, interrupts: impl Into<EnumSet<T>>);
fn pending_interrupts(&self) -> EnumSet<T>;
Expand Down
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