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esp-rs · Jan 8, 2025 · 4b41ead · 4b41ead
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diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md
@@ -97,6 +97,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - UART: Remove blocking version of `read_bytes` and rename `drain_fifo` to `read_bytes` instead (#2895)
 - Renamed variants of `CpuClock`, made the enum non-exhaustive (#2899)
 - SPI: Fix naming violations for `Mode` enum variants (#2902)
+- `macros` module is now private (#2900)
 
 ### Fixed
 

diff --git a/esp-hal/MIGRATING-0.22.md b/esp-hal/MIGRATING-0.22.md
@@ -423,3 +423,13 @@ The SPI mode variants are renamed from e.g. `Mode0` to `_0`.
 - Mode::Mode0
 + Mode::_0
 ```
+
+## `macro` module is private now
+
+Macros from `procmacros` crate (`handler`, `ram`, `load_lp_code`) are now imported via `esp-hal`.
+
+```diff
+- use esp_hal::macros::{handler, ram, load_lp_code};
++ use esp_hal::{handler, ram, load_lp_code};
+```
+
diff --git a/esp-hal/src/lib.rs b/esp-hal/src/lib.rs
@@ -143,8 +143,6 @@
 // MUST be the first module
 mod fmt;
 
-pub mod asynch;
-
 #[cfg(riscv)]
 pub use esp_riscv_rt::{self, entry, riscv};
 #[cfg(xtensa)]
@@ -156,13 +154,17 @@ pub use xtensa_lx_rt::{self, entry};
 #[cfg(any(esp32, esp32s3))]
 pub use self::soc::cpu_control;
 #[cfg(efuse)]
+#[cfg(feature = "unstable")]
 pub use self::soc::efuse;
 #[cfg(lp_core)]
+#[cfg(feature = "unstable")]
 pub use self::soc::lp_core;
 pub use self::soc::peripherals;
+#[cfg(feature = "unstable")]
 #[cfg(any(feature = "quad-psram", feature = "octal-psram"))]
 pub use self::soc::psram;
 #[cfg(ulp_riscv_core)]
+#[cfg(feature = "unstable")]
 pub use self::soc::ulp_core;
 
 #[cfg(any(dport, hp_sys, pcr, system))]
@@ -216,6 +218,7 @@ unstable_module! {
     pub mod aes;
     #[cfg(any(adc, dac))]
     pub mod analog;
+    pub mod asynch;
     #[cfg(assist_debug)]
     pub mod assist_debug;
     pub mod config;
@@ -543,7 +546,7 @@ pub fn init(config: Config) -> Peripherals {
 
     // Handle watchdog configuration with defaults
     cfg_if::cfg_if! {
-        if #[cfg(any(doc, feature = "unstable"))]
+        if #[cfg(feature = "unstable")]
         {
             #[cfg(not(any(esp32, esp32s2)))]
             if config.watchdog.swd {

diff --git a/esp-hal/src/rom/mod.rs b/esp-hal/src/rom/mod.rs
@@ -44,8 +44,6 @@ extern "C" {
     );
 }
 
-#[doc(hidden)]
-#[macro_export]
 macro_rules! regi2c_write {
     ( $block: ident, $reg_add: ident, $indata: expr ) => {
         paste::paste! {
@@ -62,10 +60,9 @@ macro_rules! regi2c_write {
     };
 }
 
-pub use regi2c_write; // TODO: can be removed as soon as ROM is stabilized
+#[allow(unused_imports)]
+pub(crate) use regi2c_write;
 
-#[doc(hidden)]
-#[macro_export]
 macro_rules! regi2c_write_mask {
     ( $block: ident, $reg_add: ident, $indata: expr ) => {
         paste::paste! {
@@ -84,7 +81,8 @@ macro_rules! regi2c_write_mask {
     };
 }
 
-pub use regi2c_write_mask; // TODO: can be removed as soon as ROM is stabilized
+#[allow(unused_imports)]
+pub(crate) use regi2c_write_mask;
 
 #[inline(always)]
 pub(crate) fn ets_delay_us(us: u32) {

diff --git a/examples/src/bin/flash_read_write.rs b/examples/src/bin/flash_read_write.rs
@@ -3,7 +3,7 @@
 //! Uses flash address 0x9000 (default NVS)
 //! See https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/partition-tables.html#built-in-partition-tables
 
-//% FEATURES: esp-storage
+//% FEATURES: esp-storage esp-hal/unstable
 //% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
 
 #![no_std]