Changelog

esp-rs · Jan 24, 2025 · 386eec8 · 386eec8
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diff --git a/esp-hal-procmacros/CHANGELOG.md b/esp-hal-procmacros/CHANGELOG.md
@@ -9,6 +9,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ### Added
 
+- Added `#[builder_lite_into]` attribute that generates the setter with `impl Into<T>` parameter (#2897)
+
 ### Changed
 
 ### Fixed

diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md
@@ -40,6 +40,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Removed features `psram-quad` and `psram-octal` - replaced by `psram` and the `ESP_HAL_CONFIG_PSRAM_MODE` (`quad`/`octal`) (#3001)
 
 - SPI and I2C `Config::frequency` has been replaced by `clock`. (#3011)
+- SPI `Config::frequency` has been replaced by `clock`. (#3011)
 - SPI `Config::with_frequency` has been renamed to `with_clock`. (#3011)
 
 ### Fixed
@@ -52,6 +53,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 - Removed `Pin`, `RtcPin` and `RtcPinWithResistors` implementations from `Flex` (#2938)
 
+- `clock_source` form `uart::Config` (#3011)
+
 ## [0.23.1] - 2025-01-15
 
 ### Fixed

diff --git a/esp-hal/MIGRATING-0.23.md b/esp-hal/MIGRATING-0.23.md
@@ -107,6 +107,44 @@ e.g.
 + uart.read_bytes(&mut byte);
 ```
 
+### UART halves have their configuration split too
+
+`Uart::Config` structure now contains separate `RxConfig` and `TxConfig`:
+
+```diff
+- let config = Config::default().with_rx_fifo_full_threshold(30);
++ let config = Config::default()
++     .with_rx(RxConfig::default()
++       .with_fifo_full_threshold(30)
++ );
+```
+
+### Changes to UART baud rate/clock source configuration
+
+UART baud rate and clock source configuration have now been grouped together in a `BaudRateConfig`
+struct. This struct implements `From<u32>`, which means if you haven't configured a clock source
+previously, you don't need to make changes to your code.
+
+The clock source configuration is now unstable, and the unstable option can be used
+by making the following code changes:
+
+```diff
++use esp_hal::uart::BaudRateConfig;
+ let mut uart = Uart::new(
+     peripherals.UART0,
+     Config::default()
+-        .with_clock_source(clock_source),
+         .with_baudrate(
+-            baud_rate,
++            BaudRateConfig::default()
++                .with_baudrate(baudrate)
++                .with_clock_source(clock_source),
++        ),
+ )
+ .unwrap();
+```
+
+
 ## `timer::wait` is now blocking
 
 ```diff
@@ -128,6 +166,20 @@ Use `DataMode::SingleTwoDataLines` to get the previous behavior.
 
 `Spi` now offers both, `with_mosi` and `with_sio0`. Consider using `with_sio` for half-duplex SPI except for [DataMode::SingleTwoDataLines] or for a mixed-bus.
 
+### SPI master driver configuration
+
+SPI `Config::with_frequency` has been renamed to `with_clock`. This function now takes either
+a `fugit::HertzU32` or `BusClockConfig`.
+
+```diff
+ let config = Config::default()
+-   .with_frequency(10.MHz());
++   .with_clock(10.MHz());
+```
+
+The new structure supports configuring a clock source, although currently only `ClockSource::Apb`
+is available.
+
 ## Removed `flip-link` Feature
 
 The `flip-link` feature is removed and replaced by the `ESP_HAL_CONFIG_FLIP_LINK` option.
@@ -162,17 +214,17 @@ config/config.toml
 + ESP_HAL_CONFIG_PSRAM_MODE = "octal"
 ```
 
+## I2C changes
 
-## UART halves have their configuration split too
+### I2C master driver configuration
 
-`Uart::Config` structure now contains separate `RxConfig` and `TxConfig`:
+SPI `Config::with_frequency` has been renamed to `with_clock`. This function now takes either
+a `fugit::HertzU32` or `BusClockConfig`.
 
 ```diff
-- let config = Config::default().with_rx_fifo_full_threshold(30);
-+ let config = Config::default()
-+     .with_rx(RxConfig::default()
-+       .with_fifo_full_threshold(30)
-+ );
+ let config = Config::default()
+-   .with_frequency(100.kHz());
++   .with_clock(100.kHz());
 ```
 
 ## GPIO changes
@@ -188,4 +240,5 @@ GPIO drivers now take configuration structs, and their constructors are fallible
 + OutputOpenDrain::new(
 +     peripherals.GPIO0,
 +     OutputOpenDrainConfig::default().with_level(Level::Low).with_pull(Pull::Up)
-+ ).unwrap();
++ ).unwrap();
+```