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target/riscv: simplify sbcs read in write_memory_bus_v1() YCAT-40267
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Change-Id: Ifc94614eaaa191925d44d8963cd6d1e5e8427cba
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en-sc committed Jun 4, 2024
1 parent b548653 commit c142c16
Showing 1 changed file with 5 additions and 10 deletions.
15 changes: 5 additions & 10 deletions src/target/riscv/riscv-013.c
Original file line number Diff line number Diff line change
Expand Up @@ -4702,27 +4702,22 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
if (result != ERROR_OK)
return result;

/* Read sbcs value.
* At the same time, detect if DMI busy has occurred during the batch write. */
bool dmi_busy_encountered;
if (dm_op(target, &sbcs, &dmi_busy_encountered, DMI_OP_READ,
DM_SBCS, 0, false, true) != ERROR_OK)
return ERROR_FAIL;
bool dmi_busy_encountered = riscv_batch_was_batch_busy(batch);
if (dmi_busy_encountered)
LOG_TARGET_DEBUG(target, "DMI busy encountered during system bus write.");

/* Wait until sbbusy goes low */
time_t start = time(NULL);
while (get_field(sbcs, DM_SBCS_SBBUSY)) {
do {
if (dm_read(target, &sbcs, DM_SBCS) != ERROR_OK)
return ERROR_FAIL;
if (time(NULL) - start > riscv_command_timeout_sec) {
LOG_TARGET_ERROR(target, "Timed out after %ds waiting for sbbusy to go low (sbcs=0x%x). "
"Increase the timeout with riscv set_command_timeout_sec.",
riscv_command_timeout_sec, sbcs);
return ERROR_FAIL;
}
if (dm_read(target, &sbcs, DM_SBCS) != ERROR_OK)
return ERROR_FAIL;
}
} while (get_field(sbcs, DM_SBCS_SBBUSY));

if (get_field(sbcs, DM_SBCS_SBBUSYERROR)) {
/* We wrote while the target was busy. */
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