Merge pull request #26 from jjsuwa-sys3175/backport-upstream

GCC: xtensa: backport patches from upstream
earlephilhower · Dec 22, 2020 · dba3cc8 · dba3cc8
2 parents 6704f5b + 064b1f2
commit dba3cc8
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Showing 12 changed files with 814 additions and 246 deletions.
diff --git a/patches/gcc10.1/gcc-repair-TARGET_ADDX.patch b/patches/gcc10.1/gcc-repair-TARGET_ADDX.patch
diff --git a/patches/gcc10.1/gcc-try-to-avoid-using-L32R-to-load-32-64bit-const.patch b/patches/gcc10.1/gcc-try-to-avoid-using-L32R-to-load-32-64bit-const.patch
diff --git a/...cc10.1/gcc-improve-shift-operations.patch → ...-optimizations-for-shift-operations.patch b/...cc10.1/gcc-improve-shift-operations.patch → ...-optimizations-for-shift-operations.patch
@@ -1,8 +1,26 @@
+From 40bf68bbe0bdba305fde4ab825a06c085ba486fc Mon Sep 17 00:00:00 2001
+From: Takayuki 'January June' Suwa <[email protected]>
+Date: Wed, 16 Dec 2020 12:53:56 -0800
+Subject: [PATCH] gcc: xtensa: add optimizations for shift operations
+
+2020-12-16  Takayuki 'January June' Suwa  <[email protected]>
+gcc/
+	* config/xtensa/xtensa.md (*ashlsi3_1, *ashlsi3_3x, *ashrsi3_3x)
+	(*lshrsi3_3x): New patterns.
+
+gcc/testsuite/
+	* gcc.target/xtensa/shifts.c: New test.
+---
+ gcc/config/xtensa/xtensa.md              | 43 ++++++++++++++++++++++++
+ gcc/testsuite/gcc.target/xtensa/shifts.c | 31 +++++++++++++++++
+ 2 files changed, 74 insertions(+)
+ create mode 100644 gcc/testsuite/gcc.target/xtensa/shifts.c
+
 diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
-index 21d60ffa..e82c466d 100644
+index 5fbe4ad4af9f..462a7244a35d 100644
 --- a/gcc/config/xtensa/xtensa.md
 +++ b/gcc/config/xtensa/xtensa.md
-@@ -1050,6 +1050,16 @@
+@@ -1071,6 +1071,16 @@
    operands[1] = xtensa_copy_incoming_a7 (operands[1]);
  })
 
@@ -19,7 +37,7 @@ index 21d60ffa..e82c466d 100644
  (define_insn "ashlsi3_internal"
    [(set (match_operand:SI 0 "register_operand" "=a,a")
  	(ashift:SI (match_operand:SI 1 "register_operand" "r,r")
-@@ -1062,6 +1072,17 @@
+@@ -1083,6 +1093,17 @@
     (set_attr "mode"	"SI")
     (set_attr "length"	"3,6")])
 
@@ -37,7 +55,7 @@ index 21d60ffa..e82c466d 100644
  (define_insn "ashrsi3"
    [(set (match_operand:SI 0 "register_operand" "=a,a")
  	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
-@@ -1074,6 +1095,17 @@
+@@ -1095,6 +1116,17 @@
     (set_attr "mode"	"SI")
     (set_attr "length"	"3,6")])
 
@@ -55,7 +73,7 @@ index 21d60ffa..e82c466d 100644
  (define_insn "lshrsi3"
    [(set (match_operand:SI 0 "register_operand" "=a,a")
  	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
-@@ -1093,6 +1125,17 @@
+@@ -1114,6 +1146,17 @@
     (set_attr "mode"	"SI")
     (set_attr "length"	"3,6")])
 
@@ -73,3 +91,40 @@ index 21d60ffa..e82c466d 100644
  (define_insn "rotlsi3"
    [(set (match_operand:SI 0 "register_operand" "=a,a")
  	(rotate:SI (match_operand:SI 1 "register_operand" "r,r")
+diff --git a/gcc/testsuite/gcc.target/xtensa/shifts.c b/gcc/testsuite/gcc.target/xtensa/shifts.c
+new file mode 100644
+index 000000000000..8d7e4a928d3a
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/xtensa/shifts.c
+@@ -0,0 +1,31 @@
++/* { dg-do compile } */
++/* { dg-options "-O1" } */
++
++int lshift1(int v)
++{
++  return v << 1;
++}
++
++int lshift2(int v, int s)
++{
++  return v << (s * 8);
++}
++
++unsigned int lshift3(unsigned int v, int s)
++{
++  return v << (s * 8);
++}
++
++int rshift1(int v, int s)
++{
++  return v >> (s * 8);
++}
++
++unsigned int rshift2(unsigned int v, int s)
++{
++  return v >> (s * 8);
++}
++
++/* { dg-final { scan-assembler-not "slli" } } */
++/* { dg-final { scan-assembler-times "ssa8l" 2 } } */
++/* { dg-final { scan-assembler-times "ssa8b" 2 } } */
diff --git a/patches/gcc10.1/gcc-xtensa-fix-PR-target-98285.patch b/patches/gcc10.1/gcc-xtensa-fix-PR-target-98285.patch
@@ -0,0 +1,137 @@
+From 06ff8708f0b834cf1b35afa46113c6c973905cad Mon Sep 17 00:00:00 2001
+From: Max Filippov <[email protected]>
+Date: Sat, 12 Dec 2020 12:14:40 -0800
+Subject: [PATCH] gcc: xtensa: fix PR target/98285
+
+2020-12-14  Max Filippov  <[email protected]>
+gcc/
+	* config/xtensa/predicates.md (addsubx_operand): Change accepted
+	values from 2/4/8 to 1..3.
+	* config/xtensa/xtensa.md (*addx, *subx): Change RTL pattern
+	to use 'ashift' instead of 'mult'. Update operands[3] value.
+
+gcc/testsuite/
+	* gcc.target/xtensa/pr98285.c: New test.
+---
+ gcc/config/xtensa/predicates.md           |  5 +--
+ gcc/config/xtensa/xtensa.md               | 18 +++++---
+ gcc/testsuite/gcc.target/xtensa/pr98285.c | 54 +++++++++++++++++++++++
+ 3 files changed, 68 insertions(+), 9 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/xtensa/pr98285.c
+
+diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md
+index 1721640dc79e..eb52b05aafad 100644
+--- a/gcc/config/xtensa/predicates.md
++++ b/gcc/config/xtensa/predicates.md
+@@ -25,9 +25,8 @@
+
+ (define_predicate "addsubx_operand"
+   (and (match_code "const_int")
+-       (match_test "INTVAL (op) == 2
+-		    || INTVAL (op) == 4
+-		    || INTVAL (op) == 8")))
++       (match_test "INTVAL (op) >= 1
++		    && INTVAL (op) <= 3")))
+
+ (define_predicate "arith_operand"
+   (ior (and (match_code "const_int")
+diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
+index 749fe477d562..671c4bea144f 100644
+--- a/gcc/config/xtensa/xtensa.md
++++ b/gcc/config/xtensa/xtensa.md
+@@ -162,11 +162,14 @@
+
+ (define_insn "*addx"
+   [(set (match_operand:SI 0 "register_operand" "=a")
+-	(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+-			  (match_operand:SI 3 "addsubx_operand" "i"))
++	(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
++			    (match_operand:SI 3 "addsubx_operand" "i"))
+ 		 (match_operand:SI 2 "register_operand" "r")))]
+   "TARGET_ADDX"
+-  "addx%3\t%0, %1, %2"
++{
++  operands[3] = GEN_INT (1 << INTVAL (operands[3]));
++  return "addx%3\t%0, %1, %2";
++}
+   [(set_attr "type"	"arith")
+    (set_attr "mode"	"SI")
+    (set_attr "length"	"3")])
+@@ -196,11 +199,14 @@
+
+ (define_insn "*subx"
+   [(set (match_operand:SI 0 "register_operand" "=a")
+-	(minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+-			   (match_operand:SI 3 "addsubx_operand" "i"))
++	(minus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
++			     (match_operand:SI 3 "addsubx_operand" "i"))
+ 		  (match_operand:SI 2 "register_operand" "r")))]
+   "TARGET_ADDX"
+-  "subx%3\t%0, %1, %2"
++{
++  operands[3] = GEN_INT (1 << INTVAL (operands[3]));
++  return "subx%3\t%0, %1, %2";
++}
+   [(set_attr "type"	"arith")
+    (set_attr "mode"	"SI")
+    (set_attr "length"	"3")])
+diff --git a/gcc/testsuite/gcc.target/xtensa/pr98285.c b/gcc/testsuite/gcc.target/xtensa/pr98285.c
+new file mode 100644
+index 000000000000..2c037d546565
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/xtensa/pr98285.c
+@@ -0,0 +1,54 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++int mul3(int v)
++{
++  return v * 3;
++}
++
++int mul5(int v)
++{
++  return v * 5;
++}
++
++int mul7(int v)
++{
++  return v * 7;
++}
++
++int mul9(int v)
++{
++  return v * 9;
++}
++
++int mul2sub(int a, int b)
++{
++  return a * 2 - b;
++}
++
++int mul4sub(int a, int b)
++{
++  return a * 4 - b;
++}
++
++short index2(short *p, int i)
++{
++  return p[i];
++}
++
++int index4(int *p, int i)
++{
++  return p[i];
++}
++
++long long index8(long long *p, int i)
++{
++  return p[i];
++}
++
++/* { dg-final { scan-assembler-times "addx2" 2 } } */
++/* { dg-final { scan-assembler-times "addx4" 2 } } */
++/* { dg-final { scan-assembler-times "addx8" 2 } } */
++/* { dg-final { scan-assembler-times "subx2" 1 } } */
++/* { dg-final { scan-assembler-times "subx4" 1 } } */
++/* { dg-final { scan-assembler-times "subx8" 1 } } */