Update database syntax

comsec-group · Jul 5, 2024 · 20a432e · 20a432e
1 parent 767b513
commit 20a432e
Show file tree

Hide file tree

Showing 7 changed files with 7 additions and 7 deletions.
diff --git a/passes/cellift/cellift.cc b/passes/cellift/cellift.cc
@@ -756,7 +756,7 @@ struct CelliftPass : public Pass {
 			for (auto cell : module->selected_cells()) {
 				RTLIL::Module *tpl = design->module(cell->type);
 				if (tpl != nullptr) {
-					if (topo_modules.database.count(tpl) == 0)
+					if (topo_modules.get_database().count(tpl) == 0)
 						worklist.push_back(tpl);
 					topo_modules.edge(tpl, module);
 					non_top_modules.insert(cell->type);

diff --git a/passes/cmds/insert_dff_cell.cc b/passes/cmds/insert_dff_cell.cc
@@ -223,7 +223,7 @@ struct InsertDffCellPass : public Pass {
 			for (auto cell : module->selected_cells()) {
 				RTLIL::Module *tpl = design->module(cell->type);
 				if (tpl != nullptr) {
-					if (topo_modules.database.count(tpl) == 0)
+					if (topo_modules.get_database().count(tpl) == 0)
 						worklist.push_back(tpl);
 					topo_modules.edge(tpl, module);
 					non_top_modules.insert(cell->type);

diff --git a/passes/cmds/insert_shift_cell.cc b/passes/cmds/insert_shift_cell.cc
@@ -132,7 +132,7 @@ struct InsertShiftCellPass : public Pass {
 			for (auto cell : module->selected_cells()) {
 				RTLIL::Module *tpl = design->module(cell->type);
 				if (tpl != nullptr) {
-					if (topo_modules.database.count(tpl) == 0)
+					if (topo_modules.get_database().count(tpl) == 0)
 						worklist.push_back(tpl);
 					topo_modules.edge(tpl, module);
 					non_top_modules.insert(cell->type);

diff --git a/passes/cmds/insert_shiftx_cell.cc b/passes/cmds/insert_shiftx_cell.cc
@@ -107,7 +107,7 @@ struct InsertShiftXCellPass : public Pass {
 			for (auto cell : module->selected_cells()) {
 				RTLIL::Module *tpl = design->module(cell->type);
 				if (tpl != nullptr) {
-					if (topo_modules.database.count(tpl) == 0)
+					if (topo_modules.get_database().count(tpl) == 0)
 						worklist.push_back(tpl);
 					topo_modules.edge(tpl, module);
 					non_top_modules.insert(cell->type);

diff --git a/passes/cmds/meta_reset.cc b/passes/cmds/meta_reset.cc
@@ -176,7 +176,7 @@ struct MetaResetPass : public Pass {
 			for (auto cell : module->selected_cells()) {
 				RTLIL::Module *tpl = design->module(cell->type);
 				if (tpl != nullptr) {
-					if (topo_modules.database.count(tpl) == 0)
+					if (topo_modules.get_database().count(tpl) == 0)
 						worklist.push_back(tpl);
 					topo_modules.edge(tpl, module);
 				}

diff --git a/passes/cmds/mul_to_adds.cc b/passes/cmds/mul_to_adds.cc
@@ -140,7 +140,7 @@ struct MulToAddsPass : public Pass {
 			for (auto cell : module->selected_cells()) {
 				RTLIL::Module *tpl = design->module(cell->type);
 				if (tpl != nullptr) {
-					if (topo_modules.database.count(tpl) == 0)
+					if (topo_modules.get_database().count(tpl) == 0)
 						worklist.push_back(tpl);
 					topo_modules.edge(tpl, module);
 					non_top_modules.insert(cell->type);

diff --git a/passes/cmds/taint_probes.cc b/passes/cmds/taint_probes.cc
@@ -188,7 +188,7 @@ struct TaintProbesPass : public Pass {
 			for (auto cell : module->selected_cells()) {
 				RTLIL::Module *tpl = design->module(cell->type);
 				if (tpl != nullptr) {
-					if (topo_modules.database.count(tpl) == 0)
+					if (topo_modules.get_database().count(tpl) == 0)
 						worklist.push_back(tpl);
 					topo_modules.edge(tpl, module);
 				}