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Merge pull request #10 from clamchowder/refactor_asmgen
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NSQ Tests
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@clamchowder
clamchowder authored Oct 21, 2023
2 parents 64e7951 + 06354be commit 952565b
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Showing 14 changed files with 543 additions and 1 deletion.
24 changes: 24 additions & 0 deletions AsmGen/Program.cs
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Expand Up @@ -37,6 +37,11 @@ static void Main(string[] args)
tests.Add(new StoreDataSchedTest(4, 64, 1));
tests.Add(new MixAddJumpSchedTest(2, 64, 1));
tests.Add(new FaddSchedTest(20, 120, 1));
tests.Add(new FcmpSchedTest(8, 120, 1));
tests.Add(new JsCvtSched(8, 120, 1));
tests.Add(new MixAddvJsCvtSched(8, 120, 1));
tests.Add(new AddvSched(8, 120, 1));
tests.Add(new FmovSched(8, 120, 1));
tests.Add(new Fadd128SchedTest(32, 80, 1));
tests.Add(new Fadd256SchedTest(4, 64, 1));
tests.Add(new Fma256SchedTest(4, 64, 1));
Expand All @@ -46,6 +51,7 @@ static void Main(string[] args)
tests.Add(new BtbTest(8, BtbTest.BranchType.Unconditional));
tests.Add(new BtbTest(16, BtbTest.BranchType.Unconditional));
tests.Add(new BtbTest(32, BtbTest.BranchType.Unconditional));
tests.Add(new BtbTest(64, BtbTest.BranchType.Unconditional));
tests.Add(new BtbTest(4, BtbTest.BranchType.Conditional));
tests.Add(new BtbTest(8, BtbTest.BranchType.Conditional));
tests.Add(new BtbTest(16, BtbTest.BranchType.Conditional));
Expand All @@ -56,6 +62,18 @@ static void Main(string[] args)
tests.Add(new BranchHistoryTest());
tests.Add(new NopLoopTest(512, 1));
tests.Add(new AddLoopTest(68, 256, 1));
/*
tests.Add(new JsCvtNsq(8, 38, 1, 40)); // a710
tests.Add(new FaddNsq(8, 48, 1, 55)); // a710
tests.Add(new MixAddvJsCvtNsq(8, 55, 1)); // a710
tests.Add(new AddvNsq(8, 38, 1, 40)); // a710
*/
tests.Add(new JsCvtNsq(8, 48, 1, 60));// x2
tests.Add(new FaddNsq(8, 48, 1, 55)); // x2
tests.Add(new MixAddvJsCvtNsq(8, 80, 1));
tests.Add(new AddvNsq(8, 48, 1, 60));
tests.Add(new StoreNsq(8, 30, 1)); // x2
tests.Add(new LoadNsq(8, 30, 1)); // x2

List<Task> tasks = new List<Task>();
tasks.Add(Task.Run(() => GenerateCFile(tests, IUarchTest.ISA.amd64)));
Expand Down Expand Up @@ -135,6 +153,12 @@ static void GenerateMakefile()
{
sb.AppendLine(isa.ToString() + ":");
sb.AppendLine($"\tgcc clammicrobench_{isa.ToString()}.c clammicrobench_{isa.ToString()}.s -o cb");
if (isa == IUarchTest.ISA.aarch64)
{
// hack for stupid compilers that need a ton of flags to do basic things
sb.AppendLine("android:");
sb.AppendLine("clang -march=armv8.3-a -mfpu=neon-fp-armv8 clammicrobench_aarch64.c clammicrobench_aarch64.s -o cb");
}
}

sb.AppendLine("win64:");
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47 changes: 47 additions & 0 deletions AsmGen/tests/AddvNsq.cs
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using System.Text;

namespace AsmGen
{
public class AddvNsq : UarchTest
{
private int totalOps;
public AddvNsq(int low, int high, int step, int totalOps)
{
this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step);
this.Prefix = "addvnsq";
this.Description = "ADDV, excluding possible NSQ";
this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr";
this.GetFunctionCallParameters = "structIterations, A, fpArr";
this.DivideTimeByCount = false;
this.totalOps = totalOps;
}

public override bool SupportsIsa(IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.aarch64) return true;
return false;
}

public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.aarch64)
{
string postLoadInstrs1 = " ldr d16, [x2, w25, sxtw #0]";
string initInstrs = " ldr d15, [x2]";
string[] depInstrs = new string[4];
depInstrs[0] = " addv h1, v16.4h";
depInstrs[1] = " addv h2, v16.4h";
depInstrs[2] = " addv h3, v16.4h";
depInstrs[3] = " addv h4, v16.4h";

string[] indepInstrs = new string[4];
indepInstrs[0] = " addv h1, v15.4h";
indepInstrs[1] = " addv h2, v15.4h";
indepInstrs[2] = " addv h3, v15.4h";
indepInstrs[3] = " addv h4, v15.4h";
UarchTestHelpers.GenerateArmAsmNsqTestFuncs(sb, this.totalOps, this.Counts, this.Prefix, depInstrs, indepInstrs, false, initInstrs,
postLoadInstrs: postLoadInstrs1);
}
}
}
}
39 changes: 39 additions & 0 deletions AsmGen/tests/AddvSchedTest.cs
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using System.Text;

namespace AsmGen
{
public class AddvSched : UarchTest
{
public AddvSched(int low, int high, int step)
{
this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step);
this.Prefix = "addvsched";
this.Description = "ADDV Scheduler";
this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr";
this.GetFunctionCallParameters = "structIterations, A, fpArr";
this.DivideTimeByCount = false;
}

public override bool SupportsIsa(IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.aarch64) return true;
return false;
}

public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.aarch64)
{
string postLoadInstrs1 = " ldr q16, [x2, w25, sxtw #0]";
string postLoadInstrs2 = " ldr q16, [x2, w25, sxtw #0]";
string[] unrolledInstrs = new string[4];
unrolledInstrs[0] = " addv h1, v16.4h";
unrolledInstrs[1] = " addv h2, v16.4h";
unrolledInstrs[2] = " addv h3, v16.4h";
unrolledInstrs[3] = " addv h4, v16.4h";
UarchTestHelpers.GenerateArmAsmStructureTestFuncs(sb, this.Counts, this.Prefix, unrolledInstrs, unrolledInstrs, false, null,
postLoadInstrs1: postLoadInstrs1, postLoadInstrs2: postLoadInstrs2);
}
}
}
}
2 changes: 1 addition & 1 deletion AsmGen/tests/BtbTest.cs
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Expand Up @@ -46,7 +46,7 @@ public enum BranchType
public BtbTest(int spacing, BranchType branchType, bool varyspacing = false)
{
this.Counts = new int[] { 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 768, 1024, 1536, 2048,
3072, 4096, 4608, 5120, 6144, 7168, 8192, 10240, 16384, 32768 };
3072, 4096, 4608, 5120, 6144, 7168, 8192, 10240, 12288, 14336, 16384, 32768 };
this.Prefix = "btb" + spacing + (varyspacing ? "v" : "") + branchType;
this.Description = $"Branch Target Buffer, " + branchType + $" branch every {spacing} bytes " + (varyspacing ? " (varied spacing)" : "");
this.FunctionDefinitionParameters = "uint64_t iterations";
Expand Down
47 changes: 47 additions & 0 deletions AsmGen/tests/FaddNsq.cs
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using System.Text;

namespace AsmGen
{
public class FaddNsq : UarchTest
{
private int totalOps;
public FaddNsq(int low, int high, int step, int totalOps)
{
this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step);
this.Prefix = "faddnsq";
this.Description = "FADD, excluding possible NSQ";
this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr";
this.GetFunctionCallParameters = "structIterations, A, fpArr";
this.DivideTimeByCount = false;
this.totalOps = totalOps;
}

public override bool SupportsIsa(IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.aarch64) return true;
return false;
}

public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.aarch64)
{
string postLoadInstrs1 = " ldr s16, [x2, w25, uxtw #2]";
string initInstrs = " ldr s15, [x2]";
string[] depInstrs = new string[4];
depInstrs[0] = " fadd s0, s0, s16";
depInstrs[1] = " fadd s1, s1, s16";
depInstrs[2] = " fadd s2, s2, s16";
depInstrs[3] = " fadd s3, s3, s16";

string[] indepInstrs = new string[4];
indepInstrs[0] = " fadd s17, s17, s15";
indepInstrs[1] = " fadd s18, s18, s15";
indepInstrs[2] = " fadd s19, s19, s15";
indepInstrs[3] = " fadd s20, s20, s15";
UarchTestHelpers.GenerateArmAsmNsqTestFuncs(sb, this.totalOps, this.Counts, this.Prefix, depInstrs, indepInstrs, false, initInstrs,
postLoadInstrs: postLoadInstrs1);
}
}
}
}
36 changes: 36 additions & 0 deletions AsmGen/tests/FcmpSchedTest.cs
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@@ -0,0 +1,36 @@
using System.Text;

namespace AsmGen
{
public class FcmpSchedTest : UarchTest
{
public FcmpSchedTest(int low, int high, int step)
{
this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step);
this.Prefix = "fcmpsched";
this.Description = "FCMP Scheduler";
this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr";
this.GetFunctionCallParameters = "structIterations, A, fpArr";
this.DivideTimeByCount = false;
}

public override bool SupportsIsa(IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.aarch64) return true;
return false;
}

public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.aarch64)
{
string[] unrolledAdds = new string[4];
unrolledAdds[0] = " fcmp s17, s16";
unrolledAdds[1] = " fcmp s19, s16";
unrolledAdds[2] = " fcmp s19, s16";
unrolledAdds[3] = " fcmp s20, s16";
UarchTestHelpers.GenerateArmAsmFpSchedTestFuncs(sb, this.Counts, this.Prefix, unrolledAdds, unrolledAdds);
}
}
}
}
39 changes: 39 additions & 0 deletions AsmGen/tests/FmovSched.cs
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@@ -0,0 +1,39 @@
using System.Text;

namespace AsmGen
{
public class FmovSched : UarchTest
{
public FmovSched(int low, int high, int step)
{
this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step);
this.Prefix = "fmovsched";
this.Description = "FMOV vec to gpr Scheduler";
this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr";
this.GetFunctionCallParameters = "structIterations, A, fpArr";
this.DivideTimeByCount = false;
}

public override bool SupportsIsa(IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.aarch64) return true;
return false;
}

public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.aarch64)
{
string postLoadInstrs1 = " ldr d16, [x2, w25, sxtw #0]";
string postLoadInstrs2 = " ldr d16, [x2, w25, sxtw #0]";
string[] unrolledInstrs = new string[4];
unrolledInstrs[0] = " fmov x15, d16";
unrolledInstrs[1] = " fmov x14, d16";
unrolledInstrs[2] = " fmov x13, d16";
unrolledInstrs[3] = " fmov x12, d16";
UarchTestHelpers.GenerateArmAsmStructureTestFuncs(sb, this.Counts, this.Prefix, unrolledInstrs, unrolledInstrs, false, null,
postLoadInstrs1: postLoadInstrs1, postLoadInstrs2: postLoadInstrs2);
}
}
}
}
47 changes: 47 additions & 0 deletions AsmGen/tests/JsCvtNsq.cs
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using System.Text;

namespace AsmGen
{
public class JsCvtNsq : UarchTest
{
private int totalOps;
public JsCvtNsq(int low, int high, int step, int totalOps)
{
this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step);
this.Prefix = "jscvtnsq";
this.Description = "FJCVTZS (FP Javascript Convert to Signed Fixed Point, Rounding toward Zero) Scheduler, excluding possible NSQ";
this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr";
this.GetFunctionCallParameters = "structIterations, A, fpArr";
this.DivideTimeByCount = false;
this.totalOps = totalOps;
}

public override bool SupportsIsa(IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.aarch64) return true;
return false;
}

public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.aarch64)
{
string postLoadInstrs1 = " ldr d16, [x2, w25, sxtw #0]";
string initInstrs = " ldr d15, [x2]";
string[] depInstrs = new string[4];
depInstrs[0] = " fjcvtzs w15, d16";
depInstrs[1] = " fjcvtzs w14, d16";
depInstrs[2] = " fjcvtzs w13, d16";
depInstrs[3] = " fjcvtzs w12, d16";

string[] indepInstrs = new string[4];
indepInstrs[0] = " fjcvtzs w15, d15";
indepInstrs[1] = " fjcvtzs w14, d15";
indepInstrs[2] = " fjcvtzs w13, d15";
indepInstrs[3] = " fjcvtzs w12, d15";
UarchTestHelpers.GenerateArmAsmNsqTestFuncs(sb, this.totalOps, this.Counts, this.Prefix, depInstrs, indepInstrs, false, initInstrs,
postLoadInstrs: postLoadInstrs1);
}
}
}
}
39 changes: 39 additions & 0 deletions AsmGen/tests/JsCvtSched.cs
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using System.Text;

namespace AsmGen
{
public class JsCvtSched : UarchTest
{
public JsCvtSched(int low, int high, int step)
{
this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step);
this.Prefix = "jscvtsched";
this.Description = "FJCVTZS (FP Javascript Convert to Signed Fixed Point, Rounding toward Zero) Scheduler";
this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr";
this.GetFunctionCallParameters = "structIterations, A, fpArr";
this.DivideTimeByCount = false;
}

public override bool SupportsIsa(IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.aarch64) return true;
return false;
}

public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.aarch64)
{
string postLoadInstrs1 = " ldr d16, [x2, w25, sxtw #0]";
string postLoadInstrs2 = " ldr d16, [x2, w25, sxtw #0]";
string[] unrolledInstrs = new string[4];
unrolledInstrs[0] = " fjcvtzs w15, d16";
unrolledInstrs[1] = " fjcvtzs w14, d16";
unrolledInstrs[2] = " fjcvtzs w13, d16";
unrolledInstrs[3] = " fjcvtzs w12, d16";
UarchTestHelpers.GenerateArmAsmStructureTestFuncs(sb, this.Counts, this.Prefix, unrolledInstrs, unrolledInstrs, false, null,
postLoadInstrs1: postLoadInstrs1, postLoadInstrs2: postLoadInstrs2);
}
}
}
}
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