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@clamchowder
clamchowder committed Aug 8, 2024
1 parent df7a8c6 commit 1f0cb47
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Showing 6 changed files with 181 additions and 26 deletions.
15 changes: 10 additions & 5 deletions AsmGen/Program.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,6 @@ static void Main(string[] args)
tests.Add(new RobTest(12, 800, 1, initialDependentBranch: false));

// avx-512
tests.Add(new Vec512RfTest(128, 600, 1));
tests.Add(new Stq512Test(16, 128, 1, differentLines: true));
tests.Add(new Stq512Test(16, 128, 1, differentLines: false));
tests.Add(new MaskRfTest(32, 256, 1));
Expand Down Expand Up @@ -58,8 +57,9 @@ static void Main(string[] args)
tests.Add(new Fadd256SchedTest(4, 200, 1));
tests.Add(new Fma256SchedTest(4, 200, 1));
tests.Add(new CvtSchedTest(64, 180, 1));
tests.Add(new Fadd128RfTest(4, 200, 1, initialDependentBranch: true));
tests.Add(new MixLdqStqTest(4, 120, 1, initialDependentBranch: true));
tests.Add(new Fadd128RfTest(200, 400, 1, false));
tests.Add(new Fadd256RfTest(200, 400, 1, Fadd256RfTest.TestMode.none));
tests.Add(new Fadd256RfTest(200, 400, 1, Fadd256RfTest.TestMode.pendingavx512instr));
tests.Add(new BtbTest(4, BtbTest.BranchType.Unconditional));
tests.Add(new BtbTest(8, BtbTest.BranchType.Unconditional));
tests.Add(new BtbTest(16, BtbTest.BranchType.Unconditional));
Expand All @@ -80,8 +80,13 @@ static void Main(string[] args)
tests.Add(new AeseSchedTest(4, 64, 1));
tests.Add(new FpStoreDataNsqTest(20, 230, 1));
tests.Add(new FpStoreDataNsqTest(10, 115, 1));
tests.Add(new FaddNsq(20, 230, 1, 230));
tests.Add(new FaddNsq(20, 115, 1, 115));
//tests.Add(new FaddNsq(20, 230, 1, 230));
//tests.Add(new FaddNsq(20, 115, 1, 115));
tests.Add(new Vec512RfTest(20, 500, 1));
tests.Add(new MixVec512Vec256RfTest(20, 500, 1));
tests.Add(new MixVec512Vec256BlockRfTest(200, 400, 1, 240));
tests.Add(new MixVec512Vec256BlockRfTest(200, 400, 1, 144));
tests.Add(new MixVec512Vec256BlockRfTest(200, 400, 1, 120));

List<Task> tasks = new List<Task>();
tasks.Add(Task.Run(() => GenerateCFile(tests, IUarchTest.ISA.amd64)));
Expand Down
34 changes: 30 additions & 4 deletions AsmGen/tests/FAdd256RfTest.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -4,14 +4,24 @@ namespace AsmGen
{
public class Fadd256RfTest : UarchTest
{
public Fadd256RfTest(int low, int high, int step)
public enum TestMode
{
none,
setavx512regs,
pendingavx512instr
}
private bool populateAvx512Regs;
private bool pendingAvx512Instr;
public Fadd256RfTest(int low, int high, int step, TestMode mode)
{
this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step);
this.Prefix = "fadd256rf";
this.Description = "256-bit FP/vector RF capacity";
this.Prefix = "fadd256rf" + mode;
this.Description = "256-bit FP/vector RF capacity, " + mode;
this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr";
this.GetFunctionCallParameters = "structIterations, A, fpArr";
this.DivideTimeByCount = false;
if (mode == TestMode.setavx512regs) populateAvx512Regs = true;
else if (mode == TestMode.pendingavx512instr) pendingAvx512Instr = true;
}

public override bool SupportsIsa(IUarchTest.ISA isa)
Expand All @@ -32,13 +42,29 @@ public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa)
" vmovups %ymm0, %ymm3\n" +
" vmovups %ymm0, %ymm4\n";

if (this.populateAvx512Regs)
{
for (int i = 5; i < 32; i++)
{
initInstrs += " vmovups 64(%r8), %zmm" + i + "\n";
}
}

string postLoadInstr = string.Empty;

if (this.pendingAvx512Instr)
{
initInstrs += " vmovups 64(%r8), %zmm5\n vmovups 128(%r8), %zmm6\n";
postLoadInstr = " vaddps %zmm5, %zmm6, %zmm6";
}

string[] unrolledAdds = new string[4];
unrolledAdds[0] = " vaddps %ymm0, %ymm1, %ymm1";
unrolledAdds[1] = " vaddps %ymm0, %ymm2, %ymm2";
unrolledAdds[2] = " vaddps %ymm0, %ymm3, %ymm3";
unrolledAdds[3] = " vaddps %ymm0, %ymm4, %ymm3";

UarchTestHelpers.GenerateX86AsmStructureTestFuncs(sb, this.Counts, this.Prefix, unrolledAdds, unrolledAdds, initInstrs: initInstrs);
UarchTestHelpers.GenerateX86AsmStructureTestFuncs(sb, this.Counts, this.Prefix, unrolledAdds, unrolledAdds, initInstrs: initInstrs, postLoadInstrs1: postLoadInstr, postLoadInstrs2: postLoadInstr);
}
else if (isa == IUarchTest.ISA.aarch64)
{
Expand Down
19 changes: 8 additions & 11 deletions AsmGen/tests/Fadd128RfTest.cs
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
using System.Text;
using System.Collections.Generic;
using System.Text;

namespace AsmGen
{
Expand Down Expand Up @@ -29,17 +30,13 @@ public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.amd64)
{
string initInstrs = " vmovups (%r8), %ymm0\n" +
" vmovups %ymm0, %ymm1\n" +
" vmovups %ymm0, %ymm2\n" +
" vmovups %ymm0, %ymm3\n" +
" vmovups %ymm0, %ymm4\n";
string initInstrs = " vmovups (%r8), %ymm0\n";

string[] unrolledAdds = new string[4];
unrolledAdds[0] = " vaddps %ymm0, %ymm1, %ymm1";
unrolledAdds[1] = " vaddps %ymm0, %ymm2, %ymm2";
unrolledAdds[2] = " vaddps %ymm0, %ymm3, %ymm3";
unrolledAdds[3] = " vaddps %ymm0, %ymm4, %ymm3";
for (int i = 1; i < 16; i++) initInstrs += $" vmovups %ymm0, %ymm{i}\n";

List<string> unrolledAddsList = new List<string>();
for (int i = 1; i < 16; i++) unrolledAddsList.Add($" vaddps %ymm0, %ymm{i}, %ymm{i}");
string[] unrolledAdds = unrolledAddsList.ToArray();

UarchTestHelpers.GenerateX86AsmStructureTestFuncs(sb, this.Counts, this.Prefix, unrolledAdds, unrolledAdds, initInstrs: initInstrs);
}
Expand Down
64 changes: 64 additions & 0 deletions AsmGen/tests/MixVec512Vec256BlockRfTest.cs
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Original file line number Diff line number Diff line change
@@ -0,0 +1,64 @@
using System.Collections.Generic;
using System.Text;

namespace AsmGen
{
public class MixVec512Vec256BlockRfTest : UarchTest
{
// number of tiny registers
private int nTiny;

public MixVec512Vec256BlockRfTest(int low, int high, int step, int nTiny)
{
this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step);
this.Prefix = "mixvec512vec256blockrf" + nTiny;
this.Description = $"Mixed zmm/ymm regs - AVX-512 only, {nTiny} 256-bit then 512-bit";
this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr";
this.GetFunctionCallParameters = "structIterations, A, fpArr";
this.DivideTimeByCount = false;
}

public override bool SupportsIsa(IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.amd64) return true;
return false;
}

public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.amd64)
{
// use even numbered regs for ymm testing
string initInstrs = " vmovups (%r8), %zmm1\n" +
" vmovups 64(%r8), %ymm2\n" +
" vmovups 128(%r8), %zmm3\n" +
" vmovups 192(%r8), %ymm4\n" +
" vmovups 256(%r8), %zmm5\n";

// use all zmm regs
for (int i = 6; i < 32; i++)
{
if ((i & 1) == 0) initInstrs += "vmovups %ymm2, %ymm" + i + "\n";
else initInstrs += "vmovups %zmm5, %zmm" + i + "\n";
}

List<string> instrsList = new List<string>();
for (int i = 0; i < nTiny; i++)
{
int regNum = ((i & 1) == 0) ? i & 0x1F : (i + 1) & 0x1F;
instrsList.Add($" vaddps %ymm2, %ymm{regNum}, %ymm{regNum}");
}

for (int i = nTiny; i < this.Counts[this.Counts.Length - 1];i++)
{
int regNum = ((i & 1) == 0) ? i: (i + 1);
regNum = (regNum + 1) & 0x1F;
instrsList.Add($" vaddps %zmm1, %zmm{regNum}, %zmm{regNum}");
}

string[] unrolledAdds = instrsList.ToArray();
UarchTestHelpers.GenerateX86AsmStructureTestFuncs(sb, this.Counts, this.Prefix, unrolledAdds, unrolledAdds, false, initInstrs);
}
}
}
}
54 changes: 54 additions & 0 deletions AsmGen/tests/MixVec512Vec256RfTest.cs
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Original file line number Diff line number Diff line change
@@ -0,0 +1,54 @@
using System.Collections.Generic;
using System.Text;

namespace AsmGen
{
public class MixVec512Vec256RfTest : UarchTest
{
public MixVec512Vec256RfTest(int low, int high, int step)
{
this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step);
this.Prefix = "mixvec512vec256rf";
this.Description = "Mixed zmm/ymm regs - AVX-512 only, alternating";
this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr";
this.GetFunctionCallParameters = "structIterations, A, fpArr";
this.DivideTimeByCount = false;
}

public override bool SupportsIsa(IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.amd64) return true;
return false;
}

public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa)
{
if (isa == IUarchTest.ISA.amd64)
{
// use even numbered regs for ymm testing
string initInstrs = " vmovups (%r8), %zmm1\n" +
" vmovups 64(%r8), %ymm2\n" +
" vmovups 128(%r8), %zmm3\n" +
" vmovups 192(%r8), %ymm4\n" +
" vmovups 256(%r8), %zmm5\n";

// use all zmm regs
for (int i = 6; i < 32; i++)
{
if ((i & 1) == 0) initInstrs += "vmovups %ymm2, %ymm" + i + "\n";
else initInstrs += "vmovups %zmm5, %zmm" + i + "\n";
}

List<string> instrsList = new List<string>();
for (int i = 1; i < 32; i++)
{
if ((i & 1) == 0) instrsList.Add($" vaddps %ymm2, %ymm{i}, %ymm{i}");
else instrsList.Add($" vaddps %zmm1, %zmm{i}, %zmm{i}");
}

string[] unrolledAdds = instrsList.ToArray();
UarchTestHelpers.GenerateX86AsmStructureTestFuncs(sb, this.Counts, this.Prefix, unrolledAdds, unrolledAdds, false, initInstrs);
}
}
}
}
21 changes: 15 additions & 6 deletions AsmGen/tests/Vec512RfTest.cs
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
using System.Text;
using System.Collections.Generic;
using System.Text;

namespace AsmGen
{
Expand Down Expand Up @@ -31,11 +32,19 @@ public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa)
" vmovups 192(%r8), %zmm4\n" +
" vmovups 256(%r8), %zmm5\n";

string[] unrolledAdds = new string[4];
unrolledAdds[0] = " vaddps %zmm1, %zmm2, %zmm2";
unrolledAdds[1] = " vaddps %zmm1, %zmm3, %zmm3";
unrolledAdds[2] = " vaddps %zmm1, %zmm4, %zmm4";
unrolledAdds[3] = " vaddps %zmm1, %zmm5, %zmm5";
// use all zmm regs
for (int i = 6; i < 32; i++)
{
initInstrs += "vmovups %zmm5, %zmm" + i + "\n";
}

List<string> instrsList = new List<string>();
for (int i = 1; i < 32; i++)
{
instrsList.Add($" vaddps %zmm1, %zmm{i}, %zmm{i}");
}

string[] unrolledAdds = instrsList.ToArray();
UarchTestHelpers.GenerateX86AsmStructureTestFuncs(sb, this.Counts, this.Prefix, unrolledAdds, unrolledAdds, false, initInstrs);
}
}
Expand Down

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