Sync master with dev #3477
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Sync master with dev #3477
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Cherry-picked chipsalliance/chisel@7372c9e Should use BarrelShifter from chisel3.std, but it is not published, see chipsalliance/chisel#2997
Ref to #2889
scala.reflect.internal.Types: constructor RecordMap in class RecordMap cannot be accessed in package util from package util in package rocketchip
It is not rs2, it is imm Related to #3255
This removes a redundant port As rnum is encoded in rs2 as imm now, we can get it just from rs2
This was introduced by "(185cac8) Add hypervisor extension (#2841)" This is a dead code, as no circuit is producing and consuming this bit. This was discovered when migrating Core.scala to chisel3, where strict checking was applied for IO and firrtl found this is not connected. In the context of hypervisor extension, V bit, or _virtualization mode_, indicates whether the hart is currently executing in a guest. For TLBReq, the V bit is needed as it affects the PTW thus TLB behavior on whether to do _Two-Stage Address Translation_. However, the bit is not needed for TLBException. The exceptions (pf, gf, ae, ma) have no V=1/V=0 variants. Also, there is no point to add V bit for gf (guest page fault). The io.resp.gf added below in the original patch also does not connect io.resp.gf.v. If this V bit should be added for this specific exception, it should be connected. I assume this was added accidentally, as the original "extends CoreBundle()(p)" modification seems irrelevant.
Also bump nix to add circt Also update arch-test script to use new isa spec of toolchain see https://lkml.org/lkml/2022/1/24/537
+ Rename `given` to `allocated`, as `given` will become a keyword in Scala 3.
Fix unconnected io.start for TLRAMXbarTest and TLMulticlientXbarTest
* implement BundleMap with new Connectable API * migrate to new BundleMap API
* remove CompileOption in Plic * remove CompileOption in tilelink Atomics * remove CompileOption in tilelink Broadcast * remove CompileOption in AsyncResetReg * remove CompileOption in LazyModule * remove CompileOption in UserYanker * remove CompileOption in FPU * fix unconnected io in DM * fix unconnected wire from DCacheModule * fix unconnected wire in ScratchpadSlavePort * handle RoCC connections * Remove NotStrictInferReset compile option
* remove import Chisel from Nodes * cloneTypeFull in BundleBrdige * better name for diplomatic node and don't care them by default
remove donttouch
- migrate to mill 0.11 - bump hardfloat and cde submodule - Cross Compile Chisel 5
Rocc csr fix
remove linting package from RegisteredLibrary
Support rocket cache rowBits != sbusWidth
add WithNoSimulationTimeout
fix PLIC 0-bit connection
add WithScratchpadsBaseAddress to alter rocket core dtim address
Fixes for latest chisel
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This synchronizes dev with master.