CSR for RoCC fix (copy #3465) #632

Job	Run time
riscv-arch-test	0s
jtag-dtm-test (freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultC...	33m 44s
jtag-dtm-test (freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultR...	37m 37s
jtag-dtm-test (freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebu...	34m 38s
jtag-dtm-test (freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebu...	37m 8s
riscv-tests (DefaultConfig)	45m 30s
riscv-tests (DefaultBufferlessConfig)	45m 58s
riscv-tests (DefaultRV32Config)	42m 33s
riscv-tests (TinyConfig)	24m 35s
riscv-tests (DefaultFP16Config)	31m 1s
emulator (DefaultSmallConfig)	29m 58s
emulator (DualBankConfig)	28m 29s
emulator (DualChannelConfig)	24m 47s
emulator (DualChannelDualBankConfig)	30m 53s
emulator (RoccExampleConfig)	30m 6s
emulator (Edge128BitConfig)	23m 51s
emulator (Edge32BitConfig)	31m 12s
emulator (QuadChannelBenchmarkConfig)	24m 10s
emulator (EightChannelConfig)	24m 24s
emulator (DualCoreConfig)	28m 52s
emulator (MemPortOnlyConfig)	27m 42s
emulator (MMIOPortOnlyConfig)	28m 58s
emulator (CloneTileConfig)	26m 4s
emulator (HypervisorConfig)	24m 1s
	11h 56m 11s

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