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@robertszczepanski @kgugala
robertszczepanski authored and kgugala committed Dec 27, 2024
1 parent 4365f80 commit eb3461e
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Showing 17 changed files with 360 additions and 197 deletions.
58 changes: 30 additions & 28 deletions src/csr/I3CCSR.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -6095,16 +6095,17 @@ module I3CCSR (
if(decoded_reg_strb.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS && decoded_req_is_wr) begin // SW write
next_c = (field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.STBY_CR_OP_RSTACT_STAT.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
load_next_c = '1;
end else begin // HW Write
end else if(hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.STBY_CR_OP_RSTACT_STAT.we) begin // HW Write - we
next_c = hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.STBY_CR_OP_RSTACT_STAT.next;
load_next_c = '1;
end
field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.STBY_CR_OP_RSTACT_STAT.next = next_c;
field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.STBY_CR_OP_RSTACT_STAT.load_next = load_next_c;
end

always_ff @(posedge clk) begin
if(field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.STBY_CR_OP_RSTACT_STAT.load_next) begin
always_ff @(posedge clk or negedge hwif_in.rst_ni) begin
if(~hwif_in.rst_ni) begin
field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.STBY_CR_OP_RSTACT_STAT.value <= 1'h0;
end else if(field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.STBY_CR_OP_RSTACT_STAT.load_next) begin
field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.STBY_CR_OP_RSTACT_STAT.value <= field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.STBY_CR_OP_RSTACT_STAT.next;
end
end
Expand Down Expand Up @@ -6417,16 +6418,17 @@ module I3CCSR (
if(decoded_reg_strb.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE && decoded_req_is_wr) begin // SW write
next_c = (field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.STBY_CR_OP_RSTACT_SIGNAL_EN.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
load_next_c = '1;
end else begin // HW Write
end else if(hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.STBY_CR_OP_RSTACT_SIGNAL_EN.we) begin // HW Write - we
next_c = hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.STBY_CR_OP_RSTACT_SIGNAL_EN.next;
load_next_c = '1;
end
field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.STBY_CR_OP_RSTACT_SIGNAL_EN.next = next_c;
field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.STBY_CR_OP_RSTACT_SIGNAL_EN.load_next = load_next_c;
end

always_ff @(posedge clk) begin
if(field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.STBY_CR_OP_RSTACT_SIGNAL_EN.load_next) begin
always_ff @(posedge clk or negedge hwif_in.rst_ni) begin
if(~hwif_in.rst_ni) begin
field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.STBY_CR_OP_RSTACT_SIGNAL_EN.value <= 1'h0;
end else if(field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.STBY_CR_OP_RSTACT_SIGNAL_EN.load_next) begin
field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.STBY_CR_OP_RSTACT_SIGNAL_EN.value <= field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.STBY_CR_OP_RSTACT_SIGNAL_EN.next;
end
end
Expand Down Expand Up @@ -6624,7 +6626,7 @@ module I3CCSR (
if(decoded_reg_strb.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE && decoded_req_is_wr) begin // SW write
next_c = (field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.STBY_CR_OP_RSTACT_FORCE.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
load_next_c = '1;
end else begin // HW Write
end else if(hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.STBY_CR_OP_RSTACT_FORCE.we) begin // HW Write - we
next_c = hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.STBY_CR_OP_RSTACT_FORCE.next;
load_next_c = '1;
end
Expand Down Expand Up @@ -6759,19 +6761,17 @@ module I3CCSR (
automatic logic load_next_c;
next_c = field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RST_ACTION.value;
load_next_c = '0;
if(decoded_reg_strb.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS && decoded_req_is_wr) begin // SW write
next_c = (field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RST_ACTION.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
load_next_c = '1;
end else begin // HW Write
if(hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RST_ACTION.we) begin // HW Write - we
next_c = hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RST_ACTION.next;
load_next_c = '1;
end
field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RST_ACTION.next = next_c;
field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RST_ACTION.load_next = load_next_c;
end

always_ff @(posedge clk) begin
if(field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RST_ACTION.load_next) begin
always_ff @(posedge clk or negedge hwif_in.rst_ni) begin
if(~hwif_in.rst_ni) begin
field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RST_ACTION.value <= 8'h0;
end else if(field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RST_ACTION.load_next) begin
field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RST_ACTION.value <= field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RST_ACTION.next;
end
end
Expand All @@ -6792,9 +6792,10 @@ module I3CCSR (
field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_PERIPHERAL.next = next_c;
field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_PERIPHERAL.load_next = load_next_c;
end

always_ff @(posedge clk) begin
if(field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_PERIPHERAL.load_next) begin
always_ff @(posedge clk or negedge hwif_in.rst_ni) begin
if(~hwif_in.rst_ni) begin
field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_PERIPHERAL.value <= 8'h0;
end else if(field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_PERIPHERAL.load_next) begin
field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_PERIPHERAL.value <= field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_PERIPHERAL.next;
end
end
Expand All @@ -6815,9 +6816,10 @@ module I3CCSR (
field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_TARGET.next = next_c;
field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_TARGET.load_next = load_next_c;
end

always_ff @(posedge clk) begin
if(field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_TARGET.load_next) begin
always_ff @(posedge clk or negedge hwif_in.rst_ni) begin
if(~hwif_in.rst_ni) begin
field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_TARGET.value <= 8'h0;
end else if(field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_TARGET.load_next) begin
field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_TARGET.value <= field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_TARGET.next;
end
end
Expand All @@ -6831,16 +6833,17 @@ module I3CCSR (
if(decoded_reg_strb.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS && decoded_req_is_wr) begin // SW write
next_c = (field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_DYNAMIC_ADDR.value & ~decoded_wr_biten[31:31]) | (decoded_wr_data[31:31] & decoded_wr_biten[31:31]);
load_next_c = '1;
end else begin // HW Write
end else if(hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_DYNAMIC_ADDR.we) begin // HW Write - we
next_c = hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_DYNAMIC_ADDR.next;
load_next_c = '1;
end
field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_DYNAMIC_ADDR.next = next_c;
field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_DYNAMIC_ADDR.load_next = load_next_c;
end

always_ff @(posedge clk) begin
if(field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_DYNAMIC_ADDR.load_next) begin
always_ff @(posedge clk or negedge hwif_in.rst_ni) begin
if(~hwif_in.rst_ni) begin
field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_DYNAMIC_ADDR.value <= 1'h1;
end else if(field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_DYNAMIC_ADDR.load_next) begin
field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_DYNAMIC_ADDR.value <= field_combo.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_DYNAMIC_ADDR.next;
end
end
Expand Down Expand Up @@ -9242,8 +9245,7 @@ module I3CCSR (
assign readback_array[69][12:12] = (decoded_reg_strb.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE && !decoded_req_is_wr) ? field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.STBY_CR_ACCEPT_NACKED_FORCE.value : '0;
assign readback_array[69][13:13] = (decoded_reg_strb.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE && !decoded_req_is_wr) ? field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.STBY_CR_ACCEPT_OK_FORCE.value : '0;
assign readback_array[69][14:14] = (decoded_reg_strb.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE && !decoded_req_is_wr) ? field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.STBY_CR_ACCEPT_ERR_FORCE.value : '0;
assign readback_array[69][15:15] = '0;
assign readback_array[69][16:16] = (decoded_reg_strb.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE && !decoded_req_is_wr) ? field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.STBY_CR_OP_RSTACT_FORCE.value : '0;
assign readback_array[69][16:15] = '0;
assign readback_array[69][17:17] = (decoded_reg_strb.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE && !decoded_req_is_wr) ? field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.CCC_PARAM_MODIFIED_FORCE.value : '0;
assign readback_array[69][18:18] = (decoded_reg_strb.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE && !decoded_req_is_wr) ? field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.CCC_UNHANDLED_NACK_FORCE.value : '0;
assign readback_array[69][19:19] = (decoded_reg_strb.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE && !decoded_req_is_wr) ? field_storage.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.CCC_FATAL_RSTDAA_ERR_FORCE.value : '0;
Expand Down
5 changes: 5 additions & 0 deletions src/csr/I3CCSR_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -673,6 +673,7 @@ package I3CCSR_pkg;

typedef struct packed{
logic next;
logic we;
} I3CCSR__I3C_EC__StdbyCtrlMode__STBY_CR_INTR_STATUS__STBY_CR_OP_RSTACT_STAT__in_t;

typedef struct packed{
Expand Down Expand Up @@ -749,6 +750,7 @@ package I3CCSR_pkg;

typedef struct packed{
logic next;
logic we;
} I3CCSR__I3C_EC__StdbyCtrlMode__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_OP_RSTACT_SIGNAL_EN__in_t;

typedef struct packed{
Expand Down Expand Up @@ -801,6 +803,7 @@ package I3CCSR_pkg;

typedef struct packed{
logic next;
logic we;
} I3CCSR__I3C_EC__StdbyCtrlMode__STBY_CR_INTR_FORCE__STBY_CR_OP_RSTACT_FORCE__in_t;

typedef struct packed{
Expand Down Expand Up @@ -842,6 +845,7 @@ package I3CCSR_pkg;

typedef struct packed{
logic [7:0] next;
logic we;
} I3CCSR__I3C_EC__StdbyCtrlMode__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RST_ACTION__in_t;

typedef struct packed{
Expand All @@ -854,6 +858,7 @@ package I3CCSR_pkg;

typedef struct packed{
logic next;
logic we;
} I3CCSR__I3C_EC__StdbyCtrlMode__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RESET_DYNAMIC_ADDR__in_t;

typedef struct packed{
Expand Down
14 changes: 7 additions & 7 deletions src/csr/I3CCSR_uvm.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3165,7 +3165,7 @@ package I3CCSR_uvm;
this.STBY_CR_ACCEPT_ERR_STAT = new("STBY_CR_ACCEPT_ERR_STAT");
this.STBY_CR_ACCEPT_ERR_STAT.configure(this, 1, 14, "RW", 1, 'h0, 0, 1, 0);
this.STBY_CR_OP_RSTACT_STAT = new("STBY_CR_OP_RSTACT_STAT");
this.STBY_CR_OP_RSTACT_STAT.configure(this, 1, 16, "RW", 1, 'h0, 0, 1, 0);
this.STBY_CR_OP_RSTACT_STAT.configure(this, 1, 16, "RW", 1, 'h0, 1, 1, 0);
this.CCC_PARAM_MODIFIED_STAT = new("CCC_PARAM_MODIFIED_STAT");
this.CCC_PARAM_MODIFIED_STAT.configure(this, 1, 17, "RW", 1, 'h0, 0, 1, 0);
this.CCC_UNHANDLED_NACK_STAT = new("CCC_UNHANDLED_NACK_STAT");
Expand Down Expand Up @@ -3285,7 +3285,7 @@ package I3CCSR_uvm;
this.STBY_CR_ACCEPT_ERR_SIGNAL_EN = new("STBY_CR_ACCEPT_ERR_SIGNAL_EN");
this.STBY_CR_ACCEPT_ERR_SIGNAL_EN.configure(this, 1, 14, "RW", 1, 'h0, 0, 1, 0);
this.STBY_CR_OP_RSTACT_SIGNAL_EN = new("STBY_CR_OP_RSTACT_SIGNAL_EN");
this.STBY_CR_OP_RSTACT_SIGNAL_EN.configure(this, 1, 16, "RW", 1, 'h0, 0, 1, 0);
this.STBY_CR_OP_RSTACT_SIGNAL_EN.configure(this, 1, 16, "RW", 1, 'h0, 1, 1, 0);
this.CCC_PARAM_MODIFIED_SIGNAL_EN = new("CCC_PARAM_MODIFIED_SIGNAL_EN");
this.CCC_PARAM_MODIFIED_SIGNAL_EN.configure(this, 1, 17, "RW", 1, 'h0, 0, 1, 0);
this.CCC_UNHANDLED_NACK_SIGNAL_EN = new("CCC_UNHANDLED_NACK_SIGNAL_EN");
Expand Down Expand Up @@ -3359,7 +3359,7 @@ package I3CCSR_uvm;
this.STBY_CR_ACCEPT_ERR_FORCE = new("STBY_CR_ACCEPT_ERR_FORCE");
this.STBY_CR_ACCEPT_ERR_FORCE.configure(this, 1, 14, "RW", 1, 'h0, 0, 1, 0);
this.STBY_CR_OP_RSTACT_FORCE = new("STBY_CR_OP_RSTACT_FORCE");
this.STBY_CR_OP_RSTACT_FORCE.configure(this, 1, 16, "RW", 1, 'h0, 0, 1, 0);
this.STBY_CR_OP_RSTACT_FORCE.configure(this, 1, 16, "WO", 1, 'h0, 0, 1, 0);
this.CCC_PARAM_MODIFIED_FORCE = new("CCC_PARAM_MODIFIED_FORCE");
this.CCC_PARAM_MODIFIED_FORCE.configure(this, 1, 17, "RW", 1, 'h0, 0, 1, 0);
this.CCC_UNHANDLED_NACK_FORCE = new("CCC_UNHANDLED_NACK_FORCE");
Expand Down Expand Up @@ -3444,13 +3444,13 @@ package I3CCSR_uvm;

virtual function void build();
this.RST_ACTION = new("RST_ACTION");
this.RST_ACTION.configure(this, 8, 0, "RW", 1, 'h0, 0, 1, 0);
this.RST_ACTION.configure(this, 8, 0, "RO", 1, 'h0, 1, 1, 0);
this.RESET_TIME_PERIPHERAL = new("RESET_TIME_PERIPHERAL");
this.RESET_TIME_PERIPHERAL.configure(this, 8, 8, "RW", 1, 'h0, 0, 1, 0);
this.RESET_TIME_PERIPHERAL.configure(this, 8, 8, "RW", 1, 'h0, 1, 1, 0);
this.RESET_TIME_TARGET = new("RESET_TIME_TARGET");
this.RESET_TIME_TARGET.configure(this, 8, 16, "RW", 1, 'h0, 0, 1, 0);
this.RESET_TIME_TARGET.configure(this, 8, 16, "RW", 1, 'h0, 1, 1, 0);
this.RESET_DYNAMIC_ADDR = new("RESET_DYNAMIC_ADDR");
this.RESET_DYNAMIC_ADDR.configure(this, 1, 31, "RW", 1, 'h0, 0, 1, 0);
this.RESET_DYNAMIC_ADDR.configure(this, 1, 31, "RW", 1, 'h1, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
foreach(RST_ACTION_bit_cg[bt]) RST_ACTION_bit_cg[bt] = new();
foreach(RESET_TIME_PERIPHERAL_bit_cg[bt]) RESET_TIME_PERIPHERAL_bit_cg[bt] = new();
Expand Down
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